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| 1 for more information www.linear.com/ltc3886 typical a pplica t ion fea t ures descrip t ion 60v dual output step-down controller with digital power system management the lt c ? 3886 is a dual polyphase dc/ dc synchronous step- down switching regulator controller with i 2 c- based pmbus compliant serial interface . this controller employs a constant- frequency, current - mode architecture, with high voltage input and output capability along with program - mable loop compensation. the ltc3886 is supported by the ltpowerplay ? software development tool with graphical user interface ( gui). the extv cc pin supports voltages up to 14 v allowing for optimized circuit efficiency and die temperature, and for the controller output to supply the chip power. switch - ing frequency, output voltage, and device address can be programmed both by digital interface as well as external configuration resistors. parameters can be set via the digital interface or stored in eeprom. both outputs have an independent power good indicator and fault function. the ltc3886 can be configured for discontinuous (pulse- skipping) mode or continuous inductor current mode. a pplica t ions n pmbus/i 2 c compliant serial interface C telemetry read-back includes v in , i in , v out , i out , temperature and faults C programmable voltage, current limit, digital soft-start/stop, sequencing, margining, ov/uv/oc, frequency, and control loop compensation n output error less than 0.5% over temperature n integrated 16- bit adc and 12- bit dac n integrated high side current sense amplifier n internal eeprom and fault logging n integrated n-channel mosfet gate drivers power conversion n wide v in range : 4.5 v to 60v n v out0 , v out1 range : 0.5 v to 13.8v n analog current mode control n accurate polyphase ? current sharing for up to 6 phases (100 khz to 750khz) n available in a 52-lead (7mm 8mm) qfn package n telecom, datacom, and storage systems n industrial and point of load applications l, lt , lt c , lt m , module, polyphase, linear technology and the linear logo are registered trademarks and ltpowerplay is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 5408150, 6580258, 6304066, 7420359, 8786268 patent pending. licensed under u.s. patent 7000125 and other related patents worldwide. load current (a) 0.01 0 efficiency (%) power loss (w) 10 30 40 50 100 70 0.1 1 3883 ta01b 20 80 90 60 0 2 9 8 7 1 4 6 5 3 10 100 v in = 48v v out = 12v f sw = 150khz efficiency and power loss vs load current intv cc tg0 tg1 boost0 boost1 sw0 sw1 bg0 fault management to/from other ltc devices sda scl alert run0 run1 extv cc v sense0 + v sense0 ? tsns0 i th0 i thr0 v sense1 tsns1 i th1 i thr1 fault0 fault1 pgood0 pgood1 bg1 share_clk 0.22f 1f 220pf 10nf 10nf v out1 12v 15a 530f 530f 3886 ta01a 4700pf v out0 5v 15a 2200pf *some details omitted for clarity 0.22f 6.81k 7.5k i sense0 + i sense1 + i sense0 ? i sense1 ? pmbus interface 10f 1f 5m 10f 2 v in 18v to 48v 0.1f 0.1f 3.1h 6.81k 7.5k 1f 1f v in ltc3886* gnd v dd33 v dd25 i in + i in ? 6.82h 1f 220pf + + ltc 3886 3886f
2 for more information www.linear.com/ltc3886 table o f c on t en t s 3886 features ..................................................... 1 applications ................................................ 1 typical application ........................................ 1 description.................................................. 1 t able of contents .......................................... 2 absolute maximum ratings .............................. 4 order information .......................................... 4 pin configuration .......................................... 4 electrical characteristics ................................. 5 typical performance characteristics .................. 10 pin functions .............................................. 13 block diagram ............................................. 15 operation................................................... 16 o verview ................................................................. 16 mai n control loop .................................................. 16 eep rom ................................................................. 17 power -up and initialization ..................................... 17 sof t-start ................................................................ 18 time- based sequencing ......................................... 18 eve nt-based sequencing ........................................ 19 shut down ............................................................... 19 lig ht-load current operation ................................. 19 pwm loop compensation ...................................... 20 swi tching frequency and phase ............................. 20 out put voltage sensing .......................................... 20 out put current sensing .......................................... 20 inp ut current sensing ............................................. 21 pol yphase load sharing ......................................... 21 ext ernal/internal temperature sense ...................... 21 rcon fig (resistor configuration) pins .................. 22 faul t handling ......................................................... 23 stat us registers and alert masking ................. 24 map ping faults to fau lt pins ............................ 24 pow er good pins ................................................ 26 crc protection .................................................. 26 seri al interface ....................................................... 26 com munication protection ................................ 26 devi ce addressing .................................................. 26 resp onses to v out and i out faults ........................ 27 out put overvoltage fault response ................... 27 out put undervoltage response ......................... 27 pea k output overcurrent fault response ........... 27 res ponses to timing faults .................................... 28 resp onses to v in ov faults .................................... 28 res ponses to ot/ut faults ..................................... 28 int ernal overtemperature fault/warn response 28 exte rnal overtemperature and undertemperature fault response .................................................. 28 resp onses to input overcurrent and output undercurrent faults ................................................ 29 res ponses to external faults ................................. 29 fau lt logging .......................................................... 29 bus t imeout protection .......................................... 29 sim ilarity between pmbus, smbus and i 2 c 2-wire interface ...................................................... 30 pmbu s serial digital interface ................................ 30 pmbus command summary ............................ 35 pmb us commands ................................................. 35 *dat a format .......................................................... 40 applications information ................................ 41 cur rent limit programming .................................... 41 i sense + and i sense C pins ......................................... 41 low va lue resistor current sensing ....................... 42 ind uctor dcr current sensing ................................ 43 slop e compensation and inductor peak current .... 44 ind uctor value calculation ...................................... 44 ind uctor core selection .......................................... 45 pow er mosfet and optional schottky diode selection ................................................................. 45 c in and c out selection ........................................... 46 var iable delay time, soft-start and output voltage ramping ................................................................. 46 dig ital servo mode ................................................. 47 sof t off (sequenced off) ........................................ 48 intv cc regulator .................................................... 48 topsi de mosfet driver supply (c b , d b ) ................ 49 fault indications ..................................................... 50 ltc 3886 3886f 3 for more information www.linear.com/ltc3886 table o f c on t en t s open-drain pins ..................................................... 50 phas e-locked loop and frequency synchronization ...................................................... 51 mini mum on-time considerations .......................... 52 external temperature sense ................................... 52 dera ting eeprom retention at temperature ...... 53 inpu t current sense amplifier ................................. 53 exte rnal resistor configuration pins (rconfig) .... 54 volt age selection ................................................ 54 fre quency selection .......................................... 55 pha se selection .................................................. 55 add ress selection using rconfig ..................... 56 eff iciency considerations ....................................... 56 pro grammable loop compensation ....................... 57 che cking transient response ................................. 57 pol yphase configuration ........................................ 58 pc bo ard layout debugging ................................... 60 desi gn example ...................................................... 62 addi tional design checks ....................................... 63 con necting the usb to i 2 c/smbus/pmbus adapter to the ltc3886 in system ......................... 63 pmbu s communication and command processing .............................................................. 65 pmbus command details ............................... 67 add ressing and write protect ................................. 67 gene ral configuration commands ........................ 69 on/ off/margin ........................................................ 70 on_of f_config .................................................... 71 pwm configuration ................................................ 72 volt age .................................................................... 76 inp ut voltage and limits ..................................... 76 out put voltage and limits .................................. 77 out put current and limits ...................................... 80 inp ut current and limits .................................... 82 temp erature ............................................................ 83 ext ernal temperature calibration ........................ 83 timing .................................................................... 84 tim ingon sequence/ramp ............................. 84 tim ingoff sequence/ramp ............................ 85 pre condition for restart ..................................... 86 fault response ....................................................... 86 fault responses all faults .................................. 86 fau lt responses input voltage ........................... 87 fau lt responses output voltage ......................... 87 fau lt responses output current ......................... 90 faul t responses ic temperature ........................ 91 fau lt responses external temperature ............... 92 fau lt sharing ........................................................... 93 fau lt sharing propagation .................................. 93 fau lt sharing response ...................................... 95 scra tchpad ............................................................. 95 ide ntification ........................................................... 96 fau lt warning and status ........................................ 97 tele metry .............................................................. 103 ee prom memory commands .............................. 106 st ore/restore ................................................... 106 fa ult logging .................................................... 107 bl ock memory write/read ................................. 111 typical applications .................................... 112 package description ................................... 115 typical application ..................................... 116 related parts ............................................ 116 ltc 3886 3886f 4 for more information www.linear.com/ltc3886 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , i in + , i in C .............................................. C0.3 v to 65 v to p gate transient voltage ( tg 0, tg 1) ....... C0.3 v to 71 v boost 0, boost1 ....................................... C0.3 v to 71 v switch transient voltage (sw 0, sw 1) .......... C5 v to 65 v int v cc , bg 0, bg 1, ( boost0C sw 0), (boost 1C sw 1) .......................................... C0.3 v to 6v v sense 0 + , v sense 1 + , i sense 0 + , i sense 1 + , i sense 0 C , i sense 1 C , extv cc ........................ C0.3 v to 15 v v sense 0 C ................................................... C0.3 v to 0. 3 v run , sda , scl , alert ............................. C0.3 v to 5.5 v asel n , v out n _ cfg , freq _ cfg , phas_ cfg , v dd 25 .................................. C0.3 v to 2 .75 v (v in C i inp ), ( v in C i inm ) ............................ C0.3 v to 0. 3 v pgood 0, pgood 1, fa u lt , share _ clk , i th 0 , i th 1 , i thr 0 , i thr 1 , v dd 33 , wp , tsns 0, tsns 1, sync ............................... C0.3 v to 3.6 v ( extv cc C v in ) ...................................................... 13.2 v int v cc peak output current ................................ 100 ma op erating junction temperature range ( n otes 2, 15, 16) .............................. C55 c to 125 c* storage temperature range ................ C65 c to 150 c* (note 1) 16 15 17 18 19 top view 53 gnd ukg package variation: ukg52(46) 52-lead (7mm 8mm) plastic qfn 20 21 22 23 24 25 26 52 50 48 47 46 44 43 42 33 35 39 36 38 40 8 7 6 5 4 2 1sw0 tg0 i sense0 + i sense0 ? tsns0 v sense0 + v sense0 ? i sense1 + i sense1 ? i thr0 i th0 sync scl boost1 sw1 tg1 tsns1 v sense1 + pgood0 pgood1 i thr1 i th1 v dd33 share_clk wp v dd25 boost0 bg0 v in i in + i in ? intv cc extv cc bg1 sda alert fault0 fault1 run0 run1 asel0 asel1 v out0_cfg v out1_cfg freq_cfg phas_cfg 32 31 30 28 27 9 10 11 12 13 14 34 29 t jmax = 125c, v ja = 31c/w, v jc = 2c/w exposed pad (pin 53) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3886eukg#pbf ltc3886eukg#trpbf ltc3886ukg 52-lead (7mm w 8mm) plastic qfn C40c to 125c ltc3886iukg#pbf ltc3886iukg#trpbf ltc3886ukg 52-lead (7mm w 8mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ * see derating eeprom retention at temperature in the applications information section for junction temperatures in excess of 125c. note: pins omitted to achieve high input voltage rating. ltc 3886 3886f 5 for more information www.linear.com/ltc3886 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t j = 25c (note 2). v in = 16v, extv cc = 0v, v run0 = 3.3v, v run1 = 3.3v f sync = 350khz (externally driven), and all programmable parameters at factory default unless otherwise specified. symbol parameter conditions min typ max units input voltage v in input voltage range (note 12) l 4.5 60 v i q input voltage supply current normal operation (note 14) v run = 3.3v, no caps on tg and bg v run = 0v 26 22 ma ma v uvlo undervoltage lockout threshold when v in > 4.2v v intvcc falling v intvcc rising 3.7 3.95 v v t init initialization time delay from restore_user_all, mfr_rest, or v intvcc > v uvlo until ton_delay can begin 70 ms control loop v outr0 range 0 maximum v out range 0 set point accuracy range 0 resolution range 0 lsb step size, fsr = 16.38 2.0v vout 13.8v (note 10) l C0.5 14.0 12 4 0.5 v % bits mv v outr1 range 1 maximum v out range 1 set point accuracy range 1 resolution range 1 lsb step size, fsr = 8.19v 1.0v v out 6.6v l C0.5 7.0 12 2 0.5 v % bits mv v linereg line regulation 16v < v in < 60v l 0.02 %/v v loadreg load regulation ?v ith = 1.35v C 0.7v ?v ith = 1.35v C 2.0v l l 0.01 C0.01 0.1 C0.1 % % g m0,1 resolution 3 bits error amplifier g m(max) i th =1.35v 5.76 mmho error amplifier g m(min) i th =1.35v 1.00 mmho error amplifier g m lsb step size i th =1.35v 0.68 mmho r ithr0,1 resolution 5 bits compensation resistor r ithr(max) 62 k compensation resistor r ithr(min) 0 k i isense input current v isense = 14v l 1 2 a v sense0(rin) v sense0 input current v pin = 14v 200 a v sense1(rin) v sense1 input current v pin = 14v 250 a v i(llimit) resolution 3 bits v ilim(max) hi range lo range l l 68 44 75 50 82 56 mv mv v ilim(min) hi range lo range 37.5 25 mv mv gate driver tg t r t f tg transition time: rise time fall time (note 4) c load = 3300pf c load = 3300pf 30 30 ns ns bg t r t f bg transition time: rise time fall time (note 4) c load = 3300pf c load = 3300pf 20 20 ns ns tg/bg t 1d top gate off to bottom gate on delay time (note 4) c load = 3300pf 10 ns bg/tg t 2d bottom gate off to top gate on delay time (note 4) c load = 3300pf 30 ns ltc 3886 3886f 6 for more information www.linear.com/ltc3886 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t j = 25c (note 2). v in = 16v, extv cc = 0v, v run0 = 3.3v, v run1 = 3.3v f sync = 350khz (externally driven), and all programmable parameters at factory default unless otherwise specified. symbol parameter conditions min typ max units t on(min) minimum on-time 90 ns ov/uv output voltage supervisor n resolution 9 bits v range0 range 0 maximum threshold 14 v v range1 range 1 maximum threshold 7 v v oustp0 range 0 step size, fsr = 16.352v (note 10) 32 mv v oustp1 range 1 step size, fsr = 8.176v 16 mv v thacc0 range 0 threshold accuracy 2v < v out < 14v l 2.5 % v thacc1 range 1 threshold accuracy 1v < v out < 7v l 2.5 % t propov1 ov comparator to fault low time v od = 10% of threshold 35 s t propuv1 uv comparator to fault low time v od = 10% of threshold 100 s v in voltage supervisor n resolution 9 bits v in(range) full-scale voltage (note 11) 4.5 61.32 v v in(stp) step size 120 mv v in(thacch) threshold accuracy 12v < v in < 60v l 3 % v in(thaccl) threshold accuracy 4.5v < v in < 15v 6 % t prop(vin) comparator response time (vin_on and vin_off) v od = 10% of threshold 100 s output voltage readback n resolution lsb step size 16 250 bits v v f/s full-scale sense voltage (note 10) v run = 0v (note 8) 16.384 v v out_tue total unadjusted error t j = 25c, v out > 1.0v (note 8) l 0.2 0.5 % % v os zero-code offset voltage l 500 v t convert conversion time (note 6) 100 ms v in voltage readback n resolution (note 5) 10 bits v f/s full-scale input voltage (note 11) 66.56 v v in_tue total unadjusted error t j = 25c, v vin > 4.5v l 0.4 2 % % t convert conversion time (note 6) 100 ms output current readback n resolution lsb step size (note 5) 0v |v isense + C v isense C | < 16mv 16mv |v isense + C v isense C | < 32mv 32mv |v isense + C v isense C | < 64mv 64mv |v isense + C v isense C | < 100mv 10 15.26 30.52 61 122 bits v v v v i f/s full-scale output current (note 7) r isense = 1m 100 a i out_tue total unadjusted error (note 8) 10mv v isense 120mv l 1.5 % v os zero-code offset voltage 32 v ltc 3886 3886f 7 for more information www.linear.com/ltc3886 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t j = 25c (note 2). v in = 16v, extv cc = 0v, v run0 = 3.3v, v run1 = 3.3v f sync = 350khz (externally driven), and all programmable parameters at factory default unless otherwise specified. symbol parameter conditions min typ max units t convert conversion time (note 6) 100 ms input current readback n resolution lsb step size, full-scale range = 16mv lsb step size, full-scale range = 32mv lsb step size, full-scale range = 64mv (note 5) 8x gain, 0v |i in + C i in C | 5mv 4x gain, 0v |i in + C i in C | 20mv 2x gain, 0v |i in + C i in C | 50mv 10 15.26 30.52 61 bits v v v i in_tue total unadjusted error (note 8) 8x gain, 2.5mv |i in + C i in C | 5mv 4x gain, 4mv |i in + C i in C | 20mv 2x gain, 6mv |i in + C i in C | 50mv l l l 1.6 1.3 1.2 % % % v os zero-code offset voltage 50 v t convert conversion time (note 6) 100 ms supply current readback n resolution lsb step size, full-scale range = 256mv (note 5) 10 244 bits v i chip_tue total unadjusted error 20mv |i in + C v in | 200mv l 2.5 % t convert conversion time (note 6) 100 ms temperature readback (t0, t1) t res_t resolution 0.25 c t0_tue external tsns tue (note 8) mfr_pwm_mode_ lt c 3886[5] = 0 mfr_pwm_mode_ lt c 3886[5] = 1 ?v tsns = 72mv (note 17) v tsns 1.85mv (note 17) l l 3 7 c c ti_tue internal tsns tue v run = 0.0v, f sync = 0khz (note 8) 1 c t convert_t update rate (note 6) 100 ms intv cc regulator v intvcc_vin internal v cc voltage no load 6v < v in < 60v l 4.8 5 5.2 v v ldo_vin intv cc load regulation i cc = 0ma to 50ma 0.5 2 % v intvcc_ext internal v cc voltage no load 5.5v < extv cc < 14v l 4.8 5 5.2 v v ldo_ext intv cc load regulation i cc = 0ma to 50ma, extv cc = 12v 0.5 2 % v ext_thres extv cc switchover voltage extv cc ramping positive l 4.5 4.7 4.9 v v ext_hys extv cc hysteresis voltage 20 mv v dd33 regulator v dd33 internal v dd33 voltage 4.5v < v intvcc 3.2 3.3 3.4 v i lim v dd33 current limit v dd33 = gnd, v in = intv cc = 4.5v 100 ma v dd33_ov v dd33 overvoltage threshold 3.5 v v dd33_uv v dd33 undervoltage threshold 3.1 v v dd25 regulator v dd25 internal v dd25 voltage 2.5 v i lim v dd25 current limit v dd25 = gnd, v in = intv cc = 4.5v 80 ma oscillator and phase-locked loop f osc oscillator frequency accuracy 100khz < f sync < 750khz measured falling edge-to-falling edge of sync with switch_frequency = 100.0 and 750.0 l 10 % v th(sync) sync input threshold v clkin falling v clkin rising 1 1.5 v v v ol(sync) sync low output voltage i load = 3ma l 0.2 0.4 v i leak(sync sync leakage current in slave mode 0v v pin 3.6v 5 a ltc 3886 3886f 8 for more information www.linear.com/ltc3886 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t j = 25c (note 2). v in = 16v, extv cc = 0v, v run0 = 3.3v, v run1 = 3.3v f sync = 350khz (externally driven), and all programmable parameters at factory default unless otherwise specified. symbol parameter conditions min typ max units sync-0 sync to channel 0 phase relationship based on the falling edge of sync and rising edge of tg0 mfr_pwm_config_ lt c 3886[2:0] = 0,2,3 mfr_pwm_config_ lt c 3886[2:0] = 5 mfr_pwm_config_ lt c 3886[2:0] = 1 mfr_pwm_config_ lt c 3886[2:0] = 4,6 0 60 90 120 deg deg deg deg sync- 1 sync to channel 1 phase relationship based on the falling edge of sync and rising edge of tg1 mfr_pwm_config_ lt c 3886[2:0] = 3 mfr_pwm_config_ lt c 3886[2:0] = 0 mfr_pwm_config_ lt c 3886[2:0] = 2,4,5 mfr_pwm_config_ltc3886[2:0] = 1 mfr_pwm_config_lt c 3886[2:0] = 6 120 180 240 270 300 deg deg deg deg deg eeprom characteristics endurance (note 13) 0c < t j < 85c during eeprom write operations l 10,000 cycles retention (note 13) t j < 125c l 10 years mass_write mass write operation time store_user_all, 0c < t j 85c during eeprom write operations l 440 4100 ms digital inputs scl, sda, runn, faultn v ih input high threshold voltage scl, sda, run, fault l 2.0 v v il input low threshold voltage scl, sda, run, fault l 1.4 v v hyst input hysteresis scl, sda 0.08 v c pin input capacitance 10 pf digital input wp i puwp input pull-up current wp 10 a open-drain outputs scl, sda, faultn, alert, runn, share_clk, pgoodn v ol output low voltage i sink = 3ma l 0.4 v digital inputs share_clk, wp v ih input high threshold voltage l 1.5 1.8 v v il input low threshold voltage l 0.6 1.0 v leakage current sda, scl, alert, run i ol input leakage current 0v v pin 5.5v l 5 a leakage current faultn, pgoodn i gl input leakage current 0v v pin 3.6v l 2 a digital filtering of faultn i fltg input digital filtering faultn 3 s digital filtering of pgoodn i fltg output digital filtering pg00dn 60 s digital filtering of runn i fltg input digital filtering runn 10 s pmbus interface timing characteristics f scl serial bus operating frequency l 10 400 khz t buf bus free time between stop and start l 1.3 s t hd( sta ) hold time after start condition. after this period, the first clock is generated l 0.6 s t su( sta ) repeated start condition setup time l 0.6 10000 s t su(sto) stop condition setup time l 0.6 s t hd( dat ) data hold time receiving data transmitting data l l 0 0.3 0.9 s s ltc 3886 3886f 9 for more information www.linear.com/ltc3886 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t j = 25c (note 2). v in = 16v, extv cc = 0v, v run0 = 3.3v, v run1 = 3.3v f sync = 350khz (externally driven), and all programmable parameters at factory default unless otherwise specified. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3886 is tested under pulsed load conditions such that t j t a . the ltc3886e is guaranteed to meet performance specifications from 0c to 85 c. specifications over the C40 c?to?125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3886i is guaranteed over the C40c to 125 c operating junction temperature range. t j is calculated from the ambient temperature, t a , and power dissipation, p d , according to the following formula: t j = t a + (p d ? ja ) the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. note 4: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 5: the data format in pmbus is 5 bits exponent (signed) and 11 bits mantissa (signed). this limits the output resolution to 10 bits though the internal adc is 16 bits and the calculations use 32-bit words. note 6: the data conversion is done in round robin fashion. all inputs signals are continuously converted for a typical latency of 100ms. note 7: the iout_cal_gain = 1.0m and mfr_iout_tc = 0.0. value as read from read_iout in amperes. note 8: part tested with pwm disabled. evaluation in application demonstrates capability. tue (%) = adc gain error (%) + 100 ? [zero code offset + adc linearity error]/actual value. note 9: all v out commands assume the adc is used to auto-zero the output to achieve the stated accuracy. ltc3886 is tested in a feedback loop that servos v out to a specified value. note 10: the maximum programmable v out voltage is 13.8v. note 11: the maximum v in voltage is 60v. note 12: when v in < 6v, intv cc must be tied to v in . note 13: eeprom endurance is guaranteed by design, characterization and correlation with statistical process controls. data retention is production tested via a high temperature bake at wafer level.the minimum retention specification applies for devices whose eeprom has been cycled less than the minimum endurance specification. the restore_user_all command (eeprom read) is valid over the entire operating temperature range. note 14: the ltc3886 quiescent current (i q ) equals the i q of v in plus the i q of extv cc . note 15: the ltc3886 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 16: write operations above t j = 85c or below 0c are possible although the electrical characteristics are not guaranteed and the eeprom will be degraded. read operations performed at temperatures between C40c and 125c will not degrade the eeprom. writing to the eeprom above 85c will result in a degradation of retention characteristics. note 17: limits guaranteed by tsns voltage and current measurements during test, including adc readback. symbol parameter conditions min typ max units t su, dat data setup time receiving data l 0.1 s t timeout_smb stuck pmbus timer non-block reads stuck pmbus timer block reads measured from the last pmbus start event 32/255 255 ms ms t low serial clock low period l 1.3 10000 s t high serial clock high period l 0.6 s ltc 3886 3886f 10 for more information www.linear.com/ltc3886 typical p er f or m ance c harac t eris t ics extv cc switchover vs temperature load step (forced continuous mode) load step (pulse-skipping mode) inductor current at light load start-up into a pre-biased load soft-start ramp efficiency vs load current, v out = 12v efficiency vs load current, v out = 5v efficiency and power loss vs input voltage load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3886 g01 0 0.1 ccm dcm v in = 48v v out = 12v f sw = 150khz l = 6.8h dcr = 1.86m load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3883 g02 0 0.1 ccm dcm v in = 48v v out = 5v f sw = 150khz l = 6.8h dcr = 1.86m v in (v) 18 94 efficiency (%) power loss (w) 95 96 97 98 2 4 6 8 10 28 38 3886 g03 48 efficiency power loss v in = 12v f sw = 150khz l = 6.8h dcr = 1.86m forced continuous mode 2a/div pulse-skipping mode 2a/div 1s/div v in = 12v v out = 1.8v i load = 100a 3886 g07 i load 5a/div inductor current 5a/div v out 100mv/div ac-coupled 50s/div v in = 12v v out = 1.8v 0.3a to 5a step 3886 g05 i load 5a/div inductor current 5a/div v out 100mv/div ac-coupled 50s/div v in = 12v v out = 1.8v 0.3a to 5a step 3886 g06 run 2v/div v out 1v/div 5ms/div t rise = 10ms t delay = 5ms v out = 2v 3886 g08 run 2v/div v out 1v/div 5ms/div t rise = 10ms t delay = 5ms 3886 g09 t a = 25c, v in = 16v, extv cc = 0v, unless otherwise noted. temperature (c) ?50 ?25 4.700 extv cc (v) 4.704 4.702 0 100 4.710 4.708 4.706 25 50 75 125 3886 g04 ltc 3886 3886f 11 for more information www.linear.com/ltc3886 typical p er f or m ance c harac t eris t ics share_clk frequency vs temperature quiescent current vs temperature v out measurement error vs v out v out command inl v out command dnl intv cc line regulation soft-off ramp regulated output voltage vs temperature maximum current sense threshold vs duty cycle, v out = 0v run 2v/div v out 1v/div 5ms/div t fall = 5ms t delay = 10ms 3886 g10 temperature (c) ?50 0.4975 v out (v) 0.4980 0.4990 0.4995 0.5000 0.5025 0.5010 0 50 75 3886 g11 0.4985 0.5015 0.5020 0.5005 ?25 25 100 125 150 duty cycle (%) 0 maximum current sense threshold (mv) 51 53 55 90 3886 g12 49 47 50 52 54 48 46 45 30 50 70 50mv sense condition temperature (c) ?50 90 share_clk frequency (khz) 95 100 105 110 ?25 0 25 50 3883 g13 75 100 125 150 temperature (c) ?50 quiescent current (ma) 24.0 24.5 25.0 25 75 3886 g14 23.5 23.0 ?25 0 50 100 125 22.5 22.0 v out (v) 0 measured error (mv) 0.2 0.4 0.6 6 10 3886 g15 0 ?0.2 2 4 8 12 14 ?0.4 ?0.6 v out (v) 0 ?1.2 inl (lsbs) ?1.0 ?0.6 ?0.4 ?0.2 0.8 0.2 4 8 3886 g16 ?0.8 0.4 0.6 0 12 16 v out (v) 0 ?0.4 dnl (lsbs) ?0.2 0 0.4 4 8 3886 g17 0.2 12 16 v in (v) 0 4.00 intv cc (v) 4.25 4.50 4.75 5.00 5.25 10 20 30 40 3886 g18 50 60 t a = 25c, v in = 16v, extv cc = 0v, unless otherwise noted. ltc 3886 3886f 12 for more information www.linear.com/ltc3886 typical p er f or m ance c harac t eris t ics external temperature error vs temperature dc output current matching in a 2-phase system (ltc3886) i out error vs i out dynamic current sharing during a load transient in a 4-phase system i in error vs i in dynamic current sharing during a load transient in a 4-phase system v out ov threshold vs temperature (1v target) v out ov threshold vs temperature (2v target) v out ov threshold vs temperature (4v target) temperature (c) ?50 0.990 1v ov threshold (v) 0.995 1.000 1.005 1.010 ?25 0 25 50 3886 g19 75 100 125 temperature (c) ?50 ?25 4.99 5v ov threshold (v) 5.00 5.00 0 100 5.02 5.01 5.01 25 50 75 125 3886 g20 temperature (c) ?50 ?25 11.98 12v ov threshold (v) 12.00 11.99 0 100 12.03 12.02 12.01 25 50 75 125 3886 g21 temperature (c) ?50 ?1.0 measurement error (c) ?0.8 ?0.4 ?0.2 0 1.0 0.4 0 50 75 3886 g22 ?0.6 0.6 0.8 0.2 ?25 25 100 125 output current (a) 0 measurement error (ma) 0 2 4 20 3886 g23 ?2 ?4 ?8 5 10 15 ?6 8 6 input current (a) 0 measurement error (ma) 0 1 2 3886 g24 ?1 ?2 ?3 1 2 3 4 5 3 total current (a) 0 channel current (a) 15 20 25 15 25 40 3886 g25 10 5 0 5 10 20 30 35 chan 0 chan 1 v in = 48v v out = 5v f sw = 150khz l = 6.8h; r sense = 3m 0a to 10a load step current 5a/div 3886 g26 10s/div current 5a/div v in = 48v v out = 5v f sw = 150khz l = 6.8h; r sense = 3m 10a to 0a load step 3886 g27 10s/div t a = 25c, v in = 16v, extv cc = 0v, unless otherwise noted. ltc 3886 3886f 13 for more information www.linear.com/ltc3886 p in func t ions sw0/sw1 (pins 1, 39): switch node connections to inductors. voltage swings at the pins are from a schottky diode (external) voltage drop below ground to v in . tg0/tg1 (pins 2, 38): top gate driver outputs. these are the outputs of floating drivers with a voltage swing equal to intv cc superimposed on the switch node voltages. i sense0 + /i sense1 + (pins 4, 9): current sense comparator inputs. the (+) input to the current comparator is normally connected to the dcr sensing network or current sensing resistor. i sense0 C /i sense1 C (pins 5, 10): current sense comparator inputs. the (C) input is connected to the output. tsns0/tsns1 (pins 6, 36): external diode temperature sense. connect to the anode of a diode-connected pnp transistor in order to sense remote temperature. directly connect the cathode using a seperate ground return path to pin 53 of the ltc3886. a bypass capacitor between the anode and cathode must be located in close proximity to the transistor. if external temperature sense elements are not installed, short pin to ground and set the ut _ fault _ limit to C275c and the ut_fault_response to ignore. v sense0 + /v sense1 + (pins 7, 35): positive output voltage sense inputs. v sense0 C (pin 8): channel 0 negative output voltage sense input. i thr0 /i thr1 (pins 11, 32): loop compensation nodes. i th0 /i th1 (pins 12, 31): current control threshold and error amplifier compensation nodes. each associated channel s current comparator tripping threshold increases with its i th voltage. sync (pin 13): external clock synchronization input and open-drain output pin. if an external clock is present at this pin, the switching frequency will be synchronized to the external clock. if clock master mode is enabled, this pin will pull low at the switching frequency with a 500 ns pulse width to ground. a resistor pull- up to 3.3 v is required in the application. scl (pin 14): serial bus clock input. open-drain output, can hold the output low if clock stretching is enabled. a pull-up resistor to 3.3v is required in the application. sda (pin 15): serial bus data input and output. a pull-up resistor to 3.3v is required in the application. alert (pin 16): open-drain digital output. connect the smbalert signal to this pin. a pull-up resistor to 3.3v is required in the application. fau lt0/ fau lt1 (pins 17, 18): digital programmable general purpose inputs and outputs. open-drain output. a pull-up resistor to 3.3v is required in the application. run0/run1 ( pins 19, 20): enable run input and output. logic high on this pin enables the controller. open-drain output holds the pin low until the ltc3886 is out of reset. this pin should be driven by an open-drain digital output. a pull-up resistor to 3.3v is required in the application. asel0/asel1 (pin 21/pin 22): serial bus address select inputs. connect optional 1% resistor dividers between v dd25 and gnd to these pins to select the serial bus interface address. refer to the applications information section for more detail. minimize capacitance when the pin is open to assure accurate detection of the pin state. v out_ cfg0 / v out_ cfg1 ( pins 23, 24): output voltage select pins. connect a 1% resistor divider between the chip v dd25 , v out_cfg and gnd in order to select output voltage. if the pin is left open, the ic will use the value programmed in the eeprom. refer to the applications information section for more detail. minimize capacitance when the pin is open to assure accurate detection of the pin state. freq_cfg (pin 25): frequency select pin. connect a 1% resistor divider between the chip v dd25 freq_cfg and gnd in order to select switching frequency. if the pin is left open, the ic will use the value programmed in the eeprom. refer to the applications information section for more detail. minimize capacitance when the pin is open to assure accurate detection of the pin state. ltc 3886 3886f 14 for more information www.linear.com/ltc3886 p in func t ions phas_cfg (pin 26): phase configuration input. connect an optional 1% resistor divider between v dd25 and gnd to this pin to configure the phase of each pwm channel relative to sync. refer to the applications information section for more detail. minimize capacitance when the pin is open to assure accurate detection of the pin state. v dd25 (pin 27): internally generated 2.5 v power sup- ply output. bypass this pin to gnd with a low esr 1f capacitor. do not load this pin externally except for the resistor dividers needed for the ltc3886 resistor con- figuration pins. wp (pin 28): write protect pin active high. an internal 10a current source pulls the pin to v dd33 . if wp is high, the pmbus writes are restricted. share_clk (pin 29): share clock, bidirectional open- drain clock sharing pin. nominally 100 khz. used to synchronize the timing between multiple ltc controllers. tie all the share_clk pins together. all lt c controllers will synchronize to the fastest clock. a pull-up resistor of 5.49k to v dd33 is required. a pull-up resistor to 3.3 v is required in the application. v dd33 (pin 30): internally generated 3.3 v power supply output. bypass this pin to gnd with a low esr 1 f capaci- tor. do not load this pin with external current. pgood0/pgood 1 ( pins 34, 33t): power good indicator outputs. open-drain logic output that is pulled to ground when the output exceeds ov/uv thresholds. the output is deglitched by an internal 100 s filter. a pull-up resistor to 3.3v is required in the application. boost1/boost0 (pins 40, 52): boosted floating driver supplies. the (+) terminal of the booststrap capacitor connects to this pin. this pin swings from a diode voltage drop below intv cc up to v in + intv cc . bg0/bg1 (pins 42, 50): bottom gate driver outputs. this pin drives the gates of the bottom n-channel mosfet between gnd and intv cc . extv cc (pin 43): external power input to an internal ldo connected to intv cc . this ldo supplies intv cc power bypassing the internal ldo powered from v in whenever extv cc is higher than 4.7 v. see extv cc connection in the applications information section. do not float or exceed 14v on this pin. decouple this pin to gnd with a minimum of 4.7 f low esr tantalum or ceramic capacitor. if the extv cc pin is not used, tie the pin to gnd. the extv cc pin may be connected to a higher voltage than the v in pin. intv cc (pin 44): internal regulator 5 v output. the control circuits are powered from this voltage. decouple this pin to gnd with a minimum of 4.7 f low esr tantalum or ceramic capacitor. i in C (pin 46): negative input of high side current sense amplifier. i in + (pin 47): positive input of high side current sense amplifier. v in (pin 48): main input supply. decouple this pin to gnd with a capacitor (0.1 f to 1 f). for applications where the main input power is 5 v, tie the v in and intv cc pins together. if the input current sense amplifier is not used, this pin must be shorted to the i in + and i in C pins. gnd ( exposed pad pin 53): ground. all small-signal and compensation components should connect to this ground, at one point. ltc 3886 3886f 15 for more information www.linear.com/ltc3886 b lock diagra m 16-bit adc pwm1 + ? ? + ? ? + + + + ? ? pwm0 ? + ? + ? + 8:1 mux tmux 2a i lim dac (3 bits) ov 9-bit ov dac 9-bit uv dac 12-bit set point dac uv ea gm i th0 r th c c2 gnd 30a ? + ? + ao r r 4r r gnd pwm clock phas_cfg freq_cfg 4r v sense + tsns0 v sense ? 4r switch logic and anti- shoot- through ov run ss uvlo rev uv on fcnt 8 7 6 26 25 v out0_cfg 23 asel0 3886 f01 21 asel1 22 17 19 c vcc bg0 d b m1 intv cc extv cc v dd33 50 i sense ? 5 i sense + 4 sw0 1 tg0 c b 2 boost0 52 v dd33 30 intv cc 44 extv cc 43 m2 c out v out + 3.3v subreg 2.5v subreg 5v reg pgood ? + ? + active clamp uvlo intv cc slope compensation slave v dd33 v stby 1.22v miso mosiclk master ram sync run0 fault0 eeprom main control program rom v dd33 compare i lim range select hi: 1:1 lo: 1:1.5 3k yr r i cmp i rev 12 i thr0 11 53 gnd c c1 + ? + ? + ? s q pwm_clock v in r vin i in ? i in + r iinsns v in c in r 9-bit v in_on threshold dac phase det v co phase selector clock divider sinc 3 uvlo ref osc (32mhz) config detect channel timing management 16 15 14 28 wp share_clk scl sda alert pmbus interface (400khz compatible) 29 48 34 sync gnd m2 gnd v dd33 13 v dd25 27 v dd25 c vcc xr ov uv pgood0 r + ? + 46 47 figure 1. block diagram, one of tw o channels (ch0) shown ltc 3886 3886f 16 for more information www.linear.com/ltc3886 o pera t ion o verview the ltc3886 is a dual channel/dual phase, constant fre- quency, analog current mode controller for dc/dc step- down applications with a digital interface. the ltc3886 digital interface is compatible with pmbus which supports bus speeds of up to 400 khz. a typical application circuit is shown on the first page of this data sheet. major features include: n programmable output voltage n programmable input voltage comparator n programmable current limit n programmable switching frequency n programmable ov and uv comparators n programmable on and off delay times n programmable output rise/fall times n programmable loop compensation n dedicated power good pin for each channel n phase- locked loop for synchronous, polyphase operation (2, 3, 4 or 6 phases) n input and output voltage/current, and temperature telemetry n fully differential remote sense on channel 0 n integrated gate drivers n nonvolatile configuration memory n optional external co nfiguration resistors for key operating parameters n optional time-base interconnect for synchronization between multiple controllers n fault logging n wp pin to protect internal eeprom configuration n standalone operation after user factory configuration n pmbus version1.2, 400khz compliant interface the pmbus inter face provides access to important power management data during system operation including: n internal die temperature n external system temperature via optional diode sense elements n average output current n average output voltage n average input voltage n average input current n configurable, latched and unlatched individual fault and warning status individual channels are accessed through the pmbus using the page command, i.e., page 0 or 1. fault reporting and shutdown behavior are fully configu - rable using the faul t n outputs. a dedicated pin for alert is provided. the shutdown operation also allows all faults to be individually masked and can be operated in either unlatched (retry) or latched modes. individual status commands enable fault reporting over the serial bus to identify the specific fault event. fault or warning detection includes the following: n output undervoltage/overvoltage n input undervoltage/overvoltage n input and output overcurrent n internal overtemperature n external overtemperature n communication, memory or logic (cml) fault m ain c ontrol l oop the ltc3886 is a constant-frequency, current-mode step- down controller that operates at a user-defined relative phasing. during normal operation the top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the i th pin which is the output of the error amplifier, ea. the ea negative terminal is equal to the v sense voltage divided by 16 (8 if range = 1). the positive terminal of the ea is ltc 3886 3886f 17 for more information www.linear.com/ltc3886 o pera t ion connected to the output of a 12- bit dac with values ranging from 0 v to 1.024 v. the output voltage, through feedback of the ea, will be regulated to 16 times the dac output (8 times if range = 1). the dac value is calculated by the part to synthesize the users desired output voltage. the output voltage is programmed by the user either with the resistor configuration pins detailed in table 3 or by the v out command ( either from eeprom, or by pmbus command). refer to the pmbus command section of the data sheet or the pmbus specification for more details. the output voltage can be modified by the user at any time with a pmbus vout_command. this command will typically have a latency less than 10ms. the user is encouraged to reference the pmbus power system management protocol specification to understand how to program the ltc3886. this specification can be found at: http://www.pmbus.org/specs.html continuing the basic operation description, the current mode controller will turn off the top gate when the peak current is reached. if the load current increases, v sense will slightly droop with respect to the dac reference. this causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on. in continuous conduction mode, the bottom mosfet stays on until the end of the switching cycle. eeprom the ltc3886 contains internal eeprom to store user configuration settings and fault log information. eeprom endurance and retention for user space and fault log pages are specified in the absolute maximum ratings and electrical characteristics table. the ltc3886 eeprom also contains a manufacturing section that has internal redundancy. the integrity of the entire onboard eeprom is checked with a crc calculation each time its data is to be read, such as after a power-on reset or execution of a restore_user_ all command. if a crc error occurs, the cml bit is set in the status_byte and status_word commands, the eeprom crc error bit in the status_mfr_specific command is set, and the alert and run pins pulled low ( pwm channels off). at that point the device will only respond at special address 0 x7c, which is activated only after an invalid crc has been detected. the chip will also respond at the global addresses 0 x5a and 0x5b, but use of these addresses when attempting to recover from a crc issue is not recommended. all power supply rails associated with either pwm channel of a device reporting an invalid crc should remain disabled until the issue is resolved. ltc recommends that the eeprom not be written when die temperature is greater than 85 c . if internal die temperature exceeds 130c , all eeprom operations except restore_user_all and mfr_reset are disabled. full eeprom operation is not re-enabled until die temperature falls below 125 c. refer to the applications information section for equations to predict retention degradation due to elevated operating temperatures. see the applications information section or contact the factory for details on efficient in- system eeprom program - ming, including bulk eeprom programming, which the ltc3886 also supports. p ower -u p and i nitiali z ation the ltc3886 is designed to provide standalone supply sequencing and controlled turn-on and turn-off operation. it can operate from a single v in input supply (4.5 v to 60v) while three on- chip linear regulators generate internal 2.5 v, 3.3v and 5 v. if v in does not exceed 6 v, and the extv cc pin is not driven by an external supply, the intv cc and v in pins must be tied together. the ltc3886 extv cc pin can driven by an external supply to improve efficiency of the circuit and minimize power on the ltc3886. the extv cc pin must exceed approximately 4.8 v before the intv cc voltage ldo operates from the extv cc pin. to minimize application power, the extv cc pin can be supplied by a switching regulator, or an output of the ltc3886. the extv cc pin voltage may exceed the v in pin voltage.the controller configuration is initialized by an internal threshold based uvlo where v in must be approximately 4.2 v and the 5v, 3.3 v and 2.5 v linear regulators must be within approximately 20% of the regulated values. a pmbus restore_user_all or mfr_reset command forces this same initialization. ltc 3886 3886f 18 for more information www.linear.com/ltc3886 o pera t ion during initialization, the external configuration resistors are identified and/or contents of the eeprom are read into the controller. the bg n , tgn , pgoodn and runn pins are held low. the fault n pins are in high impedance mode. the ltc3886 will use the contents of tables 12 to 15 to determine the resistor defined parameters. see the resistor configuration section for more detail. the resistor configuration pins only control some of the preset values of the controller. the remaining values are programmed in eeprom either at the factory or by the user. if the configuration resistors are not inserted or if the ignore rconfig bit is asserted (bit 6 of the mfr_config_ all_ lt c 3886 configuration command), the ltc3886 will use only the contents of eeprom to determine the dc/dc characteristics . the asel0 and asel1 values read at power-up or reset are always respected unless the pins are open. see the applications information section for more detail. after the part has initialized, an additional comparator monitors v in . the vin_on threshold must be exceeded before the output power sequencing can begin. after v in is initially applied, the part will typically require 70 ms to initialize and begin the ton_delay timer. the read back of voltages and currents may require an additional 200ms to 300ms. s oft -s tart the part must enter the run state prior to soft-start. the run pin is released by the ltc3886 after the part initializes and v in is greater than the vin_on threshold. if multiple ltc3886s are used in an application, they all hold their respective run pins low until all devices initialize and v in exceeds the vin_on threshold for every device. the share_clk pin assures all the devices connected to the signal use the same time base. the share_clk pin is held low until the part has initialized after v in is applied and v in exceeds the vin_on threshold. the ltc3886 can be set to turn off ( or remain off) if share_clk is low ( set bit 2 of mfr_chan_config_ltc3886 to a 1). this allows the user to assure synchronization across numerous ltc ics even if the run pins can not be connected together due to board constraints. in general, if the user cares about synchronization between chips it is best to connect all the respective run pins together and to connect all the respective share_clk pins together and pull up to v dd33 with a 10 k resistor. this assures all chips begin sequencing at the same time and use the same time base. after the run n pin releases and prior to entering a constant output voltage regulation state, the ltc3886 performs a monotonic initial ramp or soft-start. soft- start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0 v to the commanded voltage set- point. once the ltc3886 is commanded to turn on , ( after power up and initialization) the controller waits for the user specified turn-on delay (ton_delay) prior to initiating this output voltage ramp. the rise time of the voltage ramp can be programmed using the ton_ rise command to minimize inrush currents associated with the start-up voltage ramp. the soft-start feature is disabled by setting the value of ton_rise to any value less than 0.25 ms. the ltc3886 pwm always uses discontinuous mode during the ton_ rise operation. in discontinuous mode, the bottom gate is turned off as soon as reverse current is detected in the inductor. this will allow the regulator to start up into a pre-biased load. when the ton_max_fault_limit is reached, the part transitions to continuous mode, if so programmed. if ton_max_fault_limit is set to zero, there is no time limit and the part transitions to the desired conduction mode after ton_rise completes and v out has exceeded the vout_uv_fault_limit and iout_oc is not present. t ime -b ased s equencing the default mode for sequencing the output on and off is time based. the output is enabled after waiting ton _ delay amount of time following either the run n pin going high, a pmbus command to turn on, or the v in pin voltage rising above a preprogrammed voltage. off sequencing is handled in a similar way. to assure proper sequencing, make sure all ics connect the share_ clk pins together and run pins together. if the run pins can not be connected together for some reason, set bit 2 of mfr_chan_config_ltc3886 to a 1. this bit requires the share_clk pin to be clocking before the power supply output can start. when the run n pin is pulled low, the ltc3886 will hold the pin low for the mfr_restart_delay. the minimum mfr_restart_ ltc 3886 3886f 19 for more information www.linear.com/ltc3886 o pera t ion delay is toff_delay + toff_fall + 136 ms. this delay assures proper sequencing of all rails. the ltc3886 calculates this delay internally and will not process a shorter delay. however, a longer commanded mfr_restart_ delay will be used by the part. the maximum allowed value is 65.52 seconds. e vent -b ased s equencing the pgood n pin is be asserted when the output uv threshold is exceeded. it is possible to feed the pgoodn pin from one ltc3886 into the run pin of the next ltc3886 in the sequence. this can be implemented across multiple ltc3886s. if a fault in the string of rails is detected, only the faulted rail and downstream rails will fault off. the rails in the string of devices in front of the faulted rail will remain on unless commanded off. ltc3886 event-based sequencing by cascading pgoods into run pins run 1 run 0 pg0od0 pgood1 pgood0 pgood1 start ltc3886 3886 f02 run 0 to next channel in the sequence run 1 figure 2. event (voltage) based sequencing vin_off threshold or faultn pulled low externally ( if the mfr_fault_response is set to inhibit). under these conditions the power stage is disabled in order to stop the transfer of energy to the load as quickly as possible. the shutdown state can be entered from the soft-start or active regulation states either through user intervention (deasserting run or the pmbus operation command) or in response to a detected fault or an external fault via the bidirectional faultn pin, or loss of share_clk (if bit?2 of mfr_chan_config_ltc3886 is set to a 1) or v in falling below the vin_off threshold. in retry mode, the controller responds to a fault by shutting down and entering the inactive state for a programmable delay time ( mfr_retry_delay). this delay minimizes the duty cycle associated with autonomous retries if the fault that caused the shutdown disappears once the output is disabled. the retry delay time is determined by the longer of the mfr_ retry_ delay command or the time required for the regulated output to decay below 12.5% of the programmed value. if multiple outputs are controlled by the same faultn pin, the decay time of the faulted output determines the retry delay. if the natural decay time of the output is too long, it is possible to remove the voltage requirement of the mfr_retry_delay command by asserting bit 0 of mfr_ chan _ config_ lt c 3886. alterna - tively, the controller can be configured so that it remains latched-off following a fault and clearing requires user intervention such as toggling run or commanding the part off then on. l ight -l oad c urrent o peration the ltc3886 has two pwm modes of operation, discontinuous conduction mode or forced continuous conduction mode. mode selection is done using the mfr_pwm_mode_ lt c 3886 command (discontinuous conduction is always the start- up mode, forced continuous is the default running mode). if the controller is enabled for discontinuous conduction operation, the inductor current is not allowed to reverse. the reverse current comparator, i rev , turns off the bottom gate external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. s hutdown the ltc3886 supports two shutdown modes. the first mode is continuous conduction mode, with user-defined turn-off delay ( toff_delay) and ramp down rate (toff_ fall). the controller will draw current from the load to force toff_f all. the second mode is discontinuous conduction mode. in discontinous conduction mode the controller will not draw current from the load and the fall time will be set by the output capacitance and load current. the other shutdown mode occurs in response to a fault condition or loss of share_clk ( if bit 2 of mfr_chan_ config_ltc3886 is set to a 1) or v in falling below the ltc 3886 3886f 20 for more information www.linear.com/ltc3886 o pera t ion thus, the controller can operate in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined solely by the voltage on the i th pin. in this mode, the efficiency at light loads is lower than in discontinuous conduction operation. however, continuous mode exhibits lower output ripple and less interference with audio circuitry. forced continuous conduction mode may result in reverse inductor current, which can cause the input supply to boost. the vin_ov_fault_limit can detect this and turn off the offending channel. however, this fault is based on an adc read and can take up to 100 ms to detect. if there is a concern about the input supply boosting, keep the part in discontinuous conduction. pwm l oop c ompensation the internal pwm loop compensation resistors r ithn of the ltc3886 can be adjusted using bit[4:0] of the mfr_pwm_comp command. the transcondutance of the ltc3886 pwm error amplifier can be adjusted using bit[7:5] of the mfr_pwm_comp command. refer to the programmable loop compensation subsection in the applications information section for further details. s witching f requency and p hase the switching frequency of the pw m can be established with an internal oscillator or an external time base. the internal phase- locked loop ( pll) synchronizes pwm control to this timing reference with proper phase relation, whether the clock is provided internally or externally. the device can also be configured to provide the master clock to other ics through pmbus command, eeprom setting, or external configuration resistors as outlined in table 5. as clock master, the ltc3886 will drive its open-drain sync pin at the selected rate with a pulse width of 500ns. an external pull-up resistor between sync and v dd33 is required in this case. only one device connected to sync should be designated to drive the pin. if multiple ltc3886s programmed as clock masters are wired to the same sync line with a pull-up resistor, just one of the devices is automatically elected to provide clocking, and the others disable their sync outputs. the ltc3886 will automatically accept an external sync input, disabling its own sync drive if necessary. whether configured to drive sync or not, the ltc3886 can continue pwm operation using its own internal oscillator if an external clock signal is subsequently lost. the device can also be programmed to always require an external oscillator for pwm operation by setting bit 4 of mfr_config_all_ltc3886. the status of the sync driver circuit is indicated by bit 10 of mfr_pads. the mfr_pwm_config_ltc3886 command can be used to configure the phase of each channel. desired phase can also be set from eeprom or external configuration resistors as outlined in table 5. designated phase is the relationship between the falling edge of sync and the internal clock edge that sets the pwm latch to turn on the top power switch. additional small propagation delays to the pwm control pins will also apply. both channels must be off before the frequency_switch and mfr_pwm_config_ltc3886 commands can be written to the ltc3886. the phase relationships and frequency are independent of each other, providing numerous application options. multiple ltc3886 ics can be synchronized to realize a polyphase array. in this case the phases should be separated by 360/ n degrees, where n is the number of phases driving the output voltage rail. o utput v oltage s ensing the channel 0 differential amplifier allows remote, differ- ential sensing of the load voltage with v sense0n pins. the channel 1 sense pin (v sense1 ) is referenced to gnd. the (telemetry) adc is fully differential and makes measure- ments of channels 0 and 1 output voltages at the v sense0n and v sense 1 / gnd pins, respectively. the maximum allowed differential sense voltage for v sense0 + to v sense0 C is 14v. o utput c urrent s ensing for dcr current sense applications, a resistor in series with a capacitor is placed across the inductor. in this configuration, the resistor is tied to the fet side of the ltc 3886 3886f 21 for more information www.linear.com/ltc3886 o pera t ion inductor while the capacitor is tied to the load side of the inductor as shown in figure 3. if the rc values are chosen such that the rc time constant matches the inductor time constant ( l/dcr, where dcr is the inductor series resistance), the resultant voltage (v dcr ) appearing across the capacitor will equal the voltage across the inductor series resistance and thus represent the current flowing through the inductor. the rc calculations are based on the room temperature dcr of the inductor. the rc time constant should remain constant, as a function of temperature. this assures the transient response of the circuit is the same regardless of the temperature. the dcr of the inductor has a large temperature coefficient, approximately 3900 ppm/c. the temperature coefficient of the inductor must be written to the mfr_iout_cal_ gain_tc command. the external temperature is sensed near the inductor and is used to modify the internal current limit circuit to maintain an essentially constant current limit with temperature. in this application, the i sense + pin is connected to the fet side of the capacitor while the i sense C pin is placed on the load side of the capacitor. the current sensed from the input is then given by the expression v dcr /dcr. v dcr is digitized by the ltc3886s telemetry adc with an input range of 100 mv, a noise floor of 7v rms , and a peak-peak noise of approximately 46.5v . the ltc3886 computes the inductor current using the dcr value stored in the iout_cal_gain command and the temperature coefficient stored in command mfr_iout_cal_gain_tc. the resulting current value is returned by the read_iout command. i nput c urrent s ensing to sense the total input current consumed by the ltc3886 and the power stage, a resistor is placed between the supply voltage and the drain of the top n- channel mosfet. the i in + and i in C pins are connected to the sense resistor. the filtered voltage is amplified by the internal high side current sense amplifier and digitized by the ltc3886 s telemetry adc. the input current sense amplifier has three gain settings of 2x, 4 x, and 8 x set by the bit[3:2] of the mfr_ pwm_ mode_3886 command. the maximum differential input sense voltage for the three gain settings is 50mv, 20 mv, and 5 mv respectively. the ltc3886 computes the input current using the r value stored in the iin _ cal_ gain command. the resulting measured powerstage current is returned by the read _ iin command . the ltc3886 uses the rvin resistor to measure the v in pin supply current being consumed by the ltc3886. this value is returned by the mfr _ read _ ichip command. the chip current is calculated by using the r value stored in the mfr_rvin command. refer to the subsection titled input current sense amplifier in the applications information section for further detail. polyphase l oad s haring multiple ltc3886s can be connected in parallel in order to provide a balanced load-share solution by connecting the necessary pins. figure 3 illustrates the shared con - nections required for load sharing. the sync pin should only be enabled on one of the ltc3886s. the other(s) should be programmed to disable sync with the oscillator frequency set to the nominal value. when bit[5] of the mfr_pwm_config command is set, channel 1 will use the feedback node of chan - nel 0 as its point of regulation. do not assert bit[5] of mfr_pwm_config except in a polyphase application when both v out pins are connected together and both i th pins are tied together. e xternal /i nternal t emperature s ense external temperature can best be measured using a remote , diode-connected pnp transistor such as the mmbt3906. the emitter should be connected to a tsns pin while the base and collector terminals of the pnp transistor must be connected and returned directly to the pin 53 of the ltc3886 ( gnd) using a kelvin connection. the bypass capacitor between the emitter and collector must be located near the transistor. tw o different currents are applied to the diode (nominally 2 a and 32 a) and the temperature is calculated from a v be measurement made with the internal 16-bit monitor adc. the ltc3886 also supports direct v be based external temperature measurements. in this case the diode or diode network is trimmed to a specific voltage at a specific current and temperature. in general this method does not yield as accurate of a result as the single pnp transistor, ltc 3886 3886f 22 for more information www.linear.com/ltc3886 o pera t ion but may function better in noisy applications. refer to mfr_pwm_mode_ lt c 3886 in the pmbus command details section for additional information on programming the ltc3886 for these two external temperature sense configurations. the calculated temperature is returned by the pmbus read_temperature_1 command. refer to the appli - cations information section for details on proper layout of external temperature sense elements and pmbus commands that can be used to improve the accuracy of calculated temperatures. the read_ temperature_ 2 command returns the internal junction temperature of the ltc3886 using an on-chip diode with a v be measurement and calculation. rconfig (r esistor c onfiguration ) p ins there are six input pins utilizing 1% resistor dividers between v dd25 and gnd to select key operating parameters . the pins are asel0, asel1, freq _ cfg, v out0_cfg , v out1_cfg , phas _ cfg. if pins are floated, the value stored in the corresponding eeprom command is used. if bit 6 of the mfr_config_all_ltc3886 configuration command is asserted in eeprom, the resistor inputs are ignored upon power- up except for asel0 and asel1 which are always respected. the resistor configuration pins are only measured during power-up and an execution of a restore_user_all or mfr_reset command. the v outn_cfg pin settings are described in table 3. these pins select the output voltages for the ltc3886s analog pwm controllers. if the pin is open, the vout_command command is loaded from eeprom to determine the output voltage. the default setting is to have the switcher off un - less the voltage configuration pins are installed. the following parameters are set as a percentage of the output voltage if the rconfig pins are used to determined output voltage:: n vout _ ov _ fa ult _ limit .................................... +10% n vout _ ov _ war n _ limit .................................. +7. 5% n vout _ max ....................................................... +7 . 5% n vout _ margin _ hig h ......................................... +5% n vout _ margin _ low .......................................... C5% n vout _ uv _ war n _ limit .................................. C6 .5% n vout _ uv _ fa ult _ limit ...................................... C7% ltc3886 + power stage i th0 i thr0 1/2 ltc3886 + power stage i th0 v dd33 note: some connectors and components omitted for clarity i sense0 + i sense0 ? v sense0 + v sense0 ? i th1 10k fault0 run0 run1 alert fault1 sync (enabled) share_clk v dd33 pgood0 pgood1 run0 alert fault0 sync (disabled) share_clk pgood0 i sense0 + i sense0 ? i sense1 + i sense1 ? v sense1 gnd 1f gnd 3886 f03 v sense0 + v sense0 ? 1f load 10k 10k 4.99k 10k 10k run pgood share_clk alert fault sync figure 3. load sharing connections for 3-phase operation ltc 3886 3886f 23 for more information www.linear.com/ltc3886 o pera t ion the freq_cfg pin settings are described in table 4. this pin selects the switching frequency. the phase relationships between the two channels and sync pin is determined by the phas_cfg pin described in table 5. to synchronize to an external clock, the part should be put into external clock mode ( sync output disabled but frequency set to the nominal value). if no external clock is supplied, the part will clock at the programmed frequency. if the application is multi-phase and the sync signal between chips is lost, the parts will not be at the same frequency increasing the ripple voltage on the output, possibly producing undesirable operation. if the external sync signal is being generated internally and external sync is not selected, bit 10 of mfr_pads_ltc3886 will be asserted. if no frequency is selected and the external sync frequency is not present, a pll_fault will occur. if the user does not wish to see the alert from a pll_fault even if there is not a valid synchronization signal at power-up, the alert mask for pll_fault must be written. see the description on smbalert_mask for more details. if the sync pin is connected between multiple ics only one of the ics should have the sync pin enabled, all other ics should be configured to sync pin disabled. the asel0 and 1 pin settings are described in table 6. asel1 selects the top 3 bits of the slave address for the ltc3886. asel0 selects the bottom 4 bits of the slave address for the ltc3886. if asel1 is floating, the 3 most significant bits are retrieved from the eeprom mfr_address command. if asel0 is floating, the 4 lsb bits stored in eeprom mfr_address command are used to determine the 4 lsb bits of the slave address. for more detail, refer to table 6. note: per the pmbus specification, pin programmed pa - rameters can be overridden by commands from the digital interface with the exception of the asel n pins which are always honored. do not set any part address to 0 x5a or 0x5b because these are global reserved addresses and all parts will respond to them. f ault h andling a variety of fault and warning reporting and handling mechanisms are available. fault and warning detection capabilities include: n input ov/fault protection and uv warning n average input oc warn n output ov/uv fault and warn protection n output oc fault and warn protection n internal and external overtemperature fault and warn protection n external undertemperature fault and warn protection n cml fault (communication, memory or logic) n external fault detection via the bidirectional fault n pins. in addition, the ltc3886 can map any combination of fault indicators to the faultn pin using the propagate faultn response commands, mfr _ fault_ propagate_ lt c 3886. typical usage of the fault n pin is as a driver for an external crowbar device, overtemperature alert, overvoltage alert or as an interrupt to cause a microcontroller to poll the fault commands. alternatively, the fault n pin can be used as an input to detect external faults downstream of the controller that require an immediate response. as described in the soft- start section, it is possible to control start- up through concatenated events. if faultn is used to drive the run pin of another controller, the unfiltered vout_ uv fault limit should be mapped to the fault n pin. any fault or warning event will cause the alert pin to assert low unless the fault or warning is masked by the smbalert_mask. the pin will remain asserted low until the clear_faults command is issued, the fault bit is written to a 1, bias power is cycled or a mfr_reset command is issued, the run pin is toggled off/on, or the part is commanded off/on via pmbus. the mfr_ fault_propagate_ lt c 3886 command determines if the faultn pin is pulled low when a fault is detected. ltc 3886 3886f 24 for more information www.linear.com/ltc3886 o pera t ion output and input fault event handling is controlled by the corresponding fault response byte as specified in tables 5 to 9. shutdown recovery from these types of faults can either be autonomous or latched. for autonomous recovery, the faults are not latched, so if the fault condition is not present after the retry interval has elapsed, a new soft- start is attempted. if the fault persists, the controller will continue to retry. the retry interval is specified by the mfr_retry_delay command and prevents damage to the regulator components by repetitive power cycling, assuming the fault condition itself is not immediately destructive. the mfr_retry_delay must be greater than 120ms. it can not exceed 83.88 seconds. status registers and alert masking figure 4 summarizes the internal ltc3886 status registers accessible by pmbus command. these contain indication of various faults, warnings and other important operating conditions. as shown, the status_byte and status_word commands also summarize contents of other status registers. refer to pmbus command details for specific information. none of the above in status_byte indicates that one or more of the bits in the most-significant nibble of status_word are also set. in general, any asserted bit in a status_x register also pulls the alert pin low. once set, alert will remain low until one of the following occurs. n a clear_faults, restore_user_all or mfr_ reset command is issued n the related status bit is written to a one n the faulted channel is properly commanded off and back on n the ltc3886 successfully t ransmits its address during a pmbus ara n bias power is cycled with some exceptions, the smbalert_mask command can be used to prevent the ltc3886 from asserting alert for bits in these registers on a bit-by-bit basis. these mask settings apply to status_word and status_byte in the same fashion as the status bits themselves. for example, if alert is masked for all bits in channel 0 status_vout, then alert is effectively masked for the v out bit in status_word for page 0. the busy bit in status_byte also asserts alert low and cannot be masked. this bit can be set as a result of various internal interactions with pmbus communication. this fault occurs when a command is received that cannot be safely executed with one or both channels enabled. as discussed in application information, busy faults can be avoided by polling mfr_common before executing some commands. if masked faults occur immediately after power up, alert may still be pulled low because there has not been time to retrieve all of the programmed masking information from eeprom. status information contained in mfr_ common and mfr_pads can be used to further debug or clarify the contents of status_byte or status_word as shown, but the contents of these registers do not affect the state of the alert pin and may not directly influence bits in status_byte or status_word. mapping faults to fault pins the faultn pins of the ltc3886 can share faults between channels and with all ltc pmbus products including the ltc3880, ltc2974, ltc2978, ltc4676 module ? , etc. in the event of an internal fault, one or more of the ltc3886s is configured to pull the bussed faultn pins low. the other ltc3886s are then configured to shut down when the faultn pin bus is pulled low. for autonomous group retry, the faulted ltc3886 channel is configured to release the faultn pin bus after a retry interval, assuming the original fault has cleared. all the channels in the group then begin a soft-start sequence. if the fault response is latch_off, the faultn pin remains asserted low until either the run pin is toggled off/on or the part is commanded off/ on. the toggling of the run either by the pin or off/on command will clear faults associated with the ltc3886. if it is desired to have all faults cleared when either run pin is toggled, set bit 0 of mfr_config_all_ lt c 3886 to a 1. the status of all faults and warnings is summarized in the status_word and status_byte commands. ltc 3886 3886f 25 for more information www.linear.com/ltc3886 o pera t ion (paged) mfr_pads 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vdd33 ov fault vdd33 uv fault (reads 0) (reads 0) invalid adc result(s) sync clocked by external source channel 1 power good channel 0 power good ltc3886 forcing run1 low ltc3886 forcing run0 low run1 pin state run0 pin state ltc3886 forcing fault1 low ltc3886 forcing fault0 low fault pin state fault pin state status_mfr_specific 7 6 5 4 3 2 1 0 (paged) 3886 f04 status_input 7 6 5 4 3 2 1 0 status_word status_byte 7 6 5 4 3 2 1 0 (paged) mfr_common 7 6 5 4 3 2 1 0 chip not driving alert low chip not busy internal calculations not pending output not in transition eeprom initialized (reads 0) share_clk_low wp pin high status_temperature 7 6 5 4 3 2 1 0 status_cml 7 6 5 4 3 2 1 0 status_vout 7 6 5 4 3 2 1 0 (paged) status_iout 7 6 5 4 3 2 1 0 (paged) maskable description general fault or warning event general non-maskable event dynamic status derived from other bits yes no no no generates alert yes yes no not directly bit clearable yes yes no no vout_ov fault vout_ov warning vout_uv warning vout_uv fault vout_max warning ton_max fault toff_max warning (reads 0) iout_oc fault (reads 0) iout_oc warning (reads 0) (reads 0) (reads 0) (reads 0) (reads 0) ot fault ot warning (reads 0) ut fault (reads 0) (reads 0) (reads 0) (reads 0) invalid/unsupported command invalid/unsupported data packet error check failed memory fault detected processor fault detected (reads 0) other communication fault other memory or logic fault 15 14 13 12 11 10 9 8 vout iout input mfr_specific power_good# (reads 0) (reads 0) (reads 0) busy off vout_ov iout_oc (reads 0) temperature cml none of the above vin_ov fault (reads 0) vin_uv warning (reads 0) unit off for insuffcient vin (reads 0) iin_oc warning (reads 0) internal temperature fault internal temperature warning eeprom crc error internal pll unlocked fault log present vdd33 uv or ov fault vout short cycled fault pulled low by external device figure 4. ltc3886 status register summary ltc 3886 3886f 26 for more information www.linear.com/ltc3886 o pera t ion additional fault detection and handling capabilities are: power good pins the pgood n pins of the ltc3886 are connected to the open drains of internal mosfets. the mosfets turn on and pull the pgood n pins low when the channel output voltage is not within the channels uv and ov voltage thresholds. during ton_delay and ton_rise sequencing, the pg n pin is held low. the pgood n pin is also pulled low when the respective run n pin is low. the pgood n pin response is deglitched by an internal 60 s digital filter. the pgoodn pin and pgood status may be different at times due to internal communication latency of up to 10s. crc protection the integrity of the eeprom memory is checked after a power- on reset. a crc error will prevent the controller from leaving the reset state. if a crc error occurs, the cml bit is set in the status_ byte and status_ word commands, the appropriate bit is set in the status_mfr_specific command, and the alert pin will be pulled low. eeprom repair can be attempted by writing the desired configuration to the controller and executing a store_ user_ all command followed by a clear_faults command. the ltc3886 manufacturing section of the eeprom is mirrored. if both copies are corrupted, the eeprom crc fault in the status_mfr_specific command is set. if this bit remains set after being cleared by issuing a clear_faults or writing a 1 to this bit, an irrecoverable internal fault has occurred. there are no provisions for field repair of eeprom faults in the manufacturing section . s erial i nterface the ltc3886 serial interface is a pmbus compliant slave device and can operate at any frequency between 10khz and 400 khz. the address is configurable using either the eeprom or an external resistor divider. in addition the ltc3886 always responds to the global broadcast address of 0x5a (7-bit) or 0x5b (7-bit). the serial interface supports the following protocols defined in the pmbus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte, 6) read word, 7) read block , 8) write block, 9) page_plus_read, 10)? page_plus_write , 11)? smbalert_mask read and 12)? smbalert_mask. all read operations will return a valid pec if the pmbus master requests it. if the pec_ required bit is set in the mfr_config_all_ lt c 3886 command, the pmbus write operations will not be acted upon until a valid pec has been received by the ltc3886. communication protection pec write errors ( if pec_required is active), attempts to access unsupported commands, or writing invalid data to supported commands will result in a cml fault. the cml bit is set in the status_byte and status_word commands, the appropriate bit is set in the status_cml command, and the alert pin is pulled low. d evice a ddressing the ltc3886 offers four different types of addressing over the pmbus interface, specifically : 1) global, 2) device, 3) rail addressing and 4) alert response address (ara). global addressing provides a means of the pmbus master to address all ltc3886 devices on the bus. the ltc3886 global address is fixed 0 x5a (7- bit) or 0 xb4 (8- bit) and cannot be disabled. commands sent to the global address act the same as if page is set to a value of 0 xff. commands sent are written to both channels simultaneously. global command 0x5b (7- bit) or 0xb6 (8- bit) is paged and allows channel specific command of all ltc3886 devices on the bus. other lt c device types may respond at one or both of these global addresses; therefore do not read from global addresses. rail addressing provides a means for the bus master to simultaneously communicate with all channels connected together to produce a single output voltage (polyphase). while similar to global addressing, the rail address can be dynamically assigned with the paged mfr_rail_ address command , allowing for any logical grouping of channels that might be required for reliable system control. do not read from rail addresses since multiple lt c devices may respond. ltc 3886 3886f 27 for more information www.linear.com/ltc3886 device addressing provides the standard means of the pmbus master communicating with a single instance of an ltc3886. the value of the device address is set by a combination of the asel0 and asel1 configuration pins and the mfr_ address command. device address - ing can be disabled by writing a value of 0 x80 to the mfr_address. all four means of pmbus addressing require the user to employ disciplined planning to avoid addressing conflicts. communication to ltc3886 devices at global and rail ad- dresses should be limited to command write operations. r esponses to v out and i out f aults v out ov and uv conditions are monitored by comparators . the ov and uv limits are set in three ways. n as a percentage of the v out if using the resistor con- figuration pins n in eeprom if either programmed at the factory or through the gui n by pmbus command the i in and i out overcurrent monitors are performed by adc readings and calculations. thus these values are based on average currents and can have a time latency of up to 120 ms. the i out calculation accounts for the sense resistor and the temperature coefficient of the resistor. the input current is equal to the voltage measured across the r iinsns resistor divided by the resistors value as set with the mfr_rvin command. if this calculated input current exceeds the in_oc_warn_limit the alert pin is pulled low and the iin_oc_warn bit is asserted in the status_input command. the digital processor within the ltc3886 provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely ( retry). the retry interval is set in mfr_retry_delay and can be from 120 ms to 83.88 seconds in 1 ms increments. the shutdown for ov/uv and oc can be done immediately or after a user selectable deglitch time. o pera t ion output overvoltage fault response a programmable overvoltage comparator ( ov) guards against transient overshoots as well as long-term over- voltages at the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared regardless of the pmbus vout_ ov_fault_ response command byte value. this hardware level fault response delay is typically 2 s from the overvoltage condition to bg asserted high. using the vout_ov_fault_response command, the user can select any of the following behaviors: n ov pull-down only (ov cannot be ignored) n shut down (stop switching) immediatelylatch off n shut down immediatelyretry indefinitely using the time interval specified in mfr_retry_delay either the latch off or retry fault responses can be deglitched in increments of (0-7) ? 10 s. see table 7. output undervoltage response the response to an undervoltage comparator output can be either: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely using the time interval specified in mfr_retry_delay the uv responses can be deglitched. see table 8. peak output overcurrent fault response due to the current mode control algorithm, peak output current across the inductor is always limited on a cycle by cycle basis. the value of the peak current limit is specified in sense voltage in the ec table. the current limit circuit operates by limiting the i th maximum voltage. if dcr sens - ing is used, the i th maximum voltage has a temperature dependency directly proportional to the tc of the dcr of the inductor. the ltc3886 automatically monitors the external temperature sensors and modifies the maximum allowed i th to compensate for this term. ltc 3886 3886f 28 for more information www.linear.com/ltc3886 o pera t ion the overcurrent fault processing circuitry can execute the following behaviors: n current limit indefinitely n shut down immediatelylatch off n shut down immediatelyretry indefinitely using the time interval specified in mfr_retry_delay the over current responses can be deglitched in increments of (0-7) ? 16 ms. see table 9. r esponses to t iming f aults ton_max_fault_limit is the time allowed for v out to rise and settle at start-up. the ton_max_fault_limit condition is predicated upon detection of the vout_uv_ fault_limit as the output is undergoing a soft-start sequence. the ton_max_fault_limit time is started after ton_delay has been reached and a soft-start sequence is started. the resolution of the ton_max_ fault_limit is 10 s. if the vout_uv_fault_limit is not reached within the ton_max_fault_limit time, the response of this fault is determined by the value of the ton_max_fault_response command value. this response may be one of the following: n ignore n shut down (stop switching) immediatelylatch off n shut down immediatelyretry indefinitely at the time interval specified in mfr_retry_delay this fault response is not deglitched. a value of 0 in ton _max_fault_limit means the fault is ignored. the ton_max_fault_limit should be set longer than the ton_rise time. see table 11. r esponses to v in ov f aults v in overvoltage is measured with the adc. the response is deglitched by the 100 ms typical response time of the adc. the fault responses are: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely using the time interval specified in mfr_retry_delay see table 11. r esponses to ot/ut f aults internal overtemperature fault/warn response an internal temperature sensor protects against eeprom damage. above 85 c, no writes to eeprom are recommended. above 130c , the internal overtemperature warn threshold is exceeded and the part will nack any eeprom related command except restore_user_all or mfr_reset and issue a cml fault for invalid/unsup - ported command. full eeprom operation is re-enabled when the internal temperature has dropped below 125c. when the die temperature exceeds 160 c the internal overtemperature fault response is enabled and the pwm is disabled until the die temperature drops below 150c. temperature is measured by the adc. internal tempera - ture faults cannot be ignored. internal temperature limits cannot be adjusted by the user. see table 11. external overtemperature and undertemperature fault response an external temperature sensor can be used to sense critical circuit elements like the inductor and power mosfets. the ot_fault_response and ut_fault_ response commands are used to determine the appropri - ate response to a n overtemperature and undertemperature condition, respectively. if no external sense element is used (not recommended ) set the ut_fault_response to ignore and set the ut_fault_limit to C275 c. however, not using an external temperature sense element is not recommended. the fault responses are: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely using the time interval specified in mfr_retry_delay see table 11. ltc 3886 3886f 29 for more information www.linear.com/ltc3886 o pera t ion r esponses to i nput o vercurrent and o utput u ndercurrent f aults input overcurrent and output undercurrent are measured with the muxd adc. both of these measurements are deglitched by the 100 ms typical response time of the adc. the fault responses are: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely using the time interval specified in mfr_retry_delay see table 11. r esponses to e xternal f aults when either faultn pin is pulled low, the respective faultn bit is deasserted in the mfr_pads command, the faultn bit is set in the status_ mfr_ specifc command, the none_of_the_above bit is set in the status_byte command, and the alert pin is pulled low. responses are not deglitched. each channel can be configured to ignore or shut down then retry in response to its faultn pin going low by modifying the mfr_ fault_ response command. to avoid the alert pin asserting low when fault is pulled low, assert bit 1 of mfr_chan_config_ltc3886, or mask the alert using the smbalert_mask command. f ault l ogging the ltc3886 has fault logging capability. data is logged into memory in the order shown in table 13. the data is stored in a continuously upda ted buffer in ram. when a fault event occurs, the fault log buffer is copied from the ram buffer into eeprom. fault logging is allowed at temperatures above 85c ; however, retention of 10 years is not guaranteed. when the die temperature exceeds 130c, the fault logging is delayed until the die temperature drops below 125 c. the fault log data remains in eeprom until a mfr_fault_log_clear command is issued. issuing this command re - enables the fault log feature. before re - enabling fault log, be sure no faults are present and a clear_faults command has been issued. when the ltc3886 powers-up or exits reset state, it checks the eeprom for a valid fault log. if a valid fault log exists in eeprom, the valid fault log bit in the status_mfr_specific command will be set and an alert event will be generated. also, fault logging will be blocked until the ltc3886 has received a mfr_ fault_log_clear command before fault logging will be re-enabled. the information is stored in eeprom in the event of any fault that disables the controller. the fault n pin being externally pulled low will not trigger a fault logging event. b us t imeout p rotection the ltc3886 implements a timeout feature to avoid persistant faults on the serial interface. the data packet timer begins at the first start event before the device address write byte. data packet information must be completed within 30 ms or the ltc3886 will three-state the bus and ignore the given data packet. if more time is required, assert bit?3 of mfr_config_all_ lt c 3886 to allow typical bus timeouts of 255 ms. data packet infor - mation includes the device address byte write, command byte, repeat start event ( if a read operation), device address byte read ( if a read operation), all data bytes and the pec byte if applicable. the ltc3886 allows 255 ms pmbus timeouts for block read data packets. this timeout is proportional to the length of the block read. the additional block read timeout applies primarily to the mfr_fault_log command. the timeout period defaults to 32ms. the user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer between all devices sharing the serial bus interface. the ltc3886 supports the full pmbus frequency range from 10khz to 400khz. ltc 3886 3886f 30 for more information www.linear.com/ltc3886 o pera t ion s imilarity b etween pmbus, smbus and i 2 c 2-w ire i nterface the pmbus 2- wire interface is an incremental extension of the smbus. smbus is built upon i 2 c with some minor differences in timing, dc parameters and protocol. the pmbus/smbus protocols are more robust than simple i 2 c byte commands because pmbus/smbus provide time- outs to prevent persistent bus errors and optional packet error checking ( pec) to ensure data integrity. in general, a master device that can be configured for i 2 c communica- tion can be used for pmbus communication with little or no change to hardware or firmware. repeat start (restart) is not supported by all i 2 c controllers but is required for smbus/pmbus reads. if a general purpose i 2 c controller is used, check that repeat start is supported. the ltc3886 supports the maximum smbus clock speed of 100 khz and is compatible with the higher speed pmbus specification (between 100 khz and 400 khz) if mfr_common polling or clock stretching is enabled. for robust communication and operation refer to the note section in the pmbus command summary. clock stretching is enabled by assserting bit 1 of mfr_config_ all_ lt c 3886. for a description of the minor extensions and exceptions pmbus makes to smbus, refer to pmbus specification part 1 revision 1.1: paragraph 5: transport. for a description of the differences between smbus and i 2 c, refer to system management bus ( smbus) speci- fication version 2.0: appendix bdifferences between smbus and i 2 c. pmbus s erial d igital i nterface the ltc3886 communicates with a host ( master) using the standard pmbus serial bus interface. the timing diagram, figure 5, shows the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the ltc3886 is a slave device. the master can com - municate with the ltc3886 using the following formats: n master transmitter, slave receiver n master receiver, slave transmitter the following pmbus protocols are supported: n write byte, write word, send byte n read byte, read word, block read, block write n alert response address figures 6-23 illustrate the aforementioned pmbus proto- cols. all transactions support pec ( parity error check) and gcp ( group command protocol). the block read supports 255 bytes of returned data. for this reason, the pmbus timeout may be extended when reading the fault log. figure 6 is a key to the protocol diagrams in this section. pec is optional. a value shown below a field in the following figures is a mandatory value for that field. the data formats implemented by pmbus are: n master transmitter transmits to slave receiver. the transfer direction in this case is not changed. n master reads slave immediately after the first byte. at the moment of the first acknowledgment ( provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. n combined format. during a change of direction within a transfer, the master repeats both a start condition and the slave address but with the r/ w bit reversed. in this case, the master receiver terminates the transfer by generating a nack on the last byte of the transfer and a stop condition. refer to figure 6 for a legend. handshaking features are included to ensure robust system communication. please refer to the pmbus com- munication and command processing subsection of the applications information section for further details. ltc 3886 3886f 31 for more information www.linear.com/ltc3886 o pera t ion sda scl t hd(sta) t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf start condition stop condition repeated start condition start condition t r t f t r t f t high 3886 f05 figure 5. timing diagram table 1. abbreviations of supported data formats pmbus terminology specification reference lt c terminology definition example l11 linear part ii ?7.1 linear_5s_11s floating point 16-bit data: value = y ? 2 n , where n = b[15:11] and y = b[10:0], both twos compliment binary integers. b[15:0] = 0x9807 = 10011_000_0000_0111 value = 7 ? 2 C13 = 854e-6 l16 linear vout_mode part ii ?8.2 linear_16u floating point 16-bit data: value = y ???2 C12 , where y = b[15:0], an unsigned integer. b[15:0] = 0x4c00 = 0100_1100_0000_0000 value = 19456 ? 2 C12 = 4.75 cf direct part ii ?7.2 varies 16-bit data with a custom format defined in the detailed pmbus command description. often an unsigned or twos compliment integer. reg register bits part ii ?10.3 reg per-bit meaning defined in detailed pmbus command description. pmbus status_byte command. asc text characters part ii ?22.2.1 ascii iso/iec 8859-1 [a05] lt c (0x4c5443) ltc 3886 3886f 32 for more information www.linear.com/ltc3886 o pera t ion figure 7. quick command protocol figure 8. send byte protocol figure 9. send byte protocol with pec figure 6. pmbus packet protocol diagram element key figure 11. write byte protocol with pec figure 12. write word protocol figure 13. write word protocol with pec figure 10. write byte protocol 3886 f06 s start condition sr repeated start condition rd read (bit value of 1) wr write (bit value of 0) a acknowledge (this bit position may be 0 for an ack or 1 for a nack) p stop condition pec packet error code master to slave slave to master continuation of protocol ... slave address rd/wr a p 3886 f07 s 7 1 1 1 1 slave address command code wr a a p 3886 f08 s 7 8 1 1 1 1 1 slave address command code pec wr a a a p 3886 f09 s 7 8 8 1 1 1 1 1 1 slave address command code data byte wr a a a p 3886 f10 s 7 8 8 1 1 1 1 1 1 slave address command code data byte wr a a a p 3886 f11 s 7 8 8 1 pec 8 1 1 1 1 1 1 a slave address command code data byte low wr a a a p 3886 f12 s 7 8 8 1 data byte high 8 1 1 1 1 1 1 a slave address command code data byte low wr a a a p 3886 f13 s 7 8 8 1 data byte high 8 pec 8 1 1 1 1 1 1 1 a a ltc 3886 3886f 33 for more information www.linear.com/ltc3886 o pera t ion figure 17. read word protocol with pec figure 18. block read protocol figure 16. read word protocol figure 19. block read protocol with pec figure 15. read byte protocol with pec figure 14. read byte protocol slave address command code slave address wr a a sr p 3886 f14 s 7 8 11 data byte 8 1 1 1 1 1 1 1 7 a rd a slave address command code slave address wr a a sr p 3886 f15 s 7 8 7 11 data byte 8 1 1 1 1 1 1 1 a rd a 1 a pec slave address command code slave address wr a a a p 3886 f16 s 7 8 7 1 data byte low 8 data byte high 8 1 1 1 1 sr 1 1 1 1 a 1 rd a slave address command code slave address wr a a a pa 3886 f17 s 7 8 7 1 data byte low 8 data byte high pec 8 8 1 1 1 1 1 11 1 sr 1 a 1 rd a slave address command code slave address wr a a sr s 7 8 7 11 byte count = n 8 1 1 1 1 1 1 a rd a ? a pa 3886 f18 data byte 1 8 data byte 2 data byte n 8 8 1 1 11 a ? ? slave address command code slave address wr a a sr s 7 8 7 11 byte count = n 8 1 1 1 1 1 1 a rd a ? ? ? a data byte 1 8 data byte 2 8 1 1 a a pa 3886 f19 data byte n pec 8 8 1 11 ltc 3886 3886f 34 for more information www.linear.com/ltc3886 o pera t ion figure 20. block write C block read process call figure 22. alert response address protocol figure 23. alert response address protocol with pec figure 21. block write C block read process call with pec slave address command code byte count = m wr a a s 7 8 8 1 data byte 1 8 1 1 1 1 1 a a ? ? a data byte 2 8 1 a data byte m 8 1 slave address byte count = n rd a a sr 7 8 data byte 1 8 1 1 1 1 1 1 a ? p 3886 f20 1 ? ? ? a data byte 2 8 1 a data byte n 8 1 slave address command code byte count = m wr a a s 7 8 8 1 data byte 1 8 1 1 1 1 1 a a ? ? a data byte 2 8 1 a data byte m 8 1 slave address byte count = n rd a a sr 7 8 data byte 1 8 1 1 1 1 1 1 a ? ? ? ? a data byte 2 8 1 a data byte n 8 1 p 3886 f21 1 a pec 8 1 alert response address rd a a p 3886 f22 s 7 8 1 1 1 1 1 device address alert response address rd a a s 7 8 1 1 1 1 device address a p 3886 f23 8 1 1 pec ltc 3886 3886f 35 for more information www.linear.com/ltc3886 p m b us c o mm an d s u mm ary pmbus c ommands the following tables list supported pmbus commands and manufacturer specific commands. a complete description of these commands can be found in the pmbus power system mgt protocol specification C part ii C revision 1.2. users are encouraged to reference this specification. exceptions or manufacturer specific implementations are listed below in table 2. floating point values listed in the default value column are either linear 16-bit signed ( pmbus section 8.3.1) or linear_5s_11s (pmbus section 7.1) format, whichever is appropriate for the com - mand. all commands from 0 xd0 through 0 xff not listed in this table are implicitly reserved by the manufacturer. users should avoid blind writes within this range of com - mands to avoid undesired operation of the part. all com- mands from 0x00 through 0 xcf not listed in this table are implicitly not supported by the manufacturer. attempting to access non-supported or reserved commands may result in a cml command fault event. all output voltage settings and measurements are based on the vout_mode setting of 0x14. this translates to an exponent of 2 C12 . if pmbus commands are received faster than they are be- ing processed , the part may become too busy to handle new commands. in these circumstances the part follows the protocols defined in the pmbus specification v1.1, part?ii, section 10.8.7, to communicate that it is busy. the part includes handshaking features to eliminate busy errors and simplify error handling software while ensur - ing robust communication and system behavior. please refer to the subsection titled pmbus communication and command processing in the applications information section for further details. table 2. summary ( note: the data format abbreviations are detailed at the end of this table.) command name cmd code description type paged d ata format units eeprom default value page page 0x00 provides integration with multi-page pmbus devices. r/w byte n reg 0x00 67 operation 0x01 operating mode control. on/off, margin high and margin low. r/w byte y reg y 0x40 71 on_off_config 0x02 run pin and pmbus bus on/off command configuration. r/w byte y reg y 0x1e 71 clear_faults 0x03 clear any fault bits that have been set. send byte n na 97 page_plus_write 0x05 write a command directly to a specified page. w block n 67 page_plus_read 0x06 read a command directly from a specified page. block r/w n 68 write_protect 0x10 level of protection provided by the device against accidental changes. r/w byte n reg y 0x00 68 store_user_all 0x15 store user operating memory to eeprom. send byte n na 107 restore_user_all 0x16 restore user operating memory from eeprom. send byte n na 107 capability 0x19 summary of pmbus optional communication protocols supported by this device. r byte n reg 0xb0 96 smbalert_mask 0x1b mask alert activity block r/w y reg y see cmd 97 vout_mode 0x20 output voltage format and exponent (2 C12 ). r byte y reg 2 C12 0x14 78 vout_command 0x21 nominal output voltage set point. r/w word y l16 v y 1.0 0x1000 79 vout_max 0x24 upper limit on the commanded output voltage including vout_margin_hi. r/w word y l16 v y 14.0 0xe000 78 vout_margin_high 0x25 margin high output voltage set point. must be greater than vout_command. r/w word y l16 v y 1.05 0x10cd 79 ltc 3886 3886f 36 for more information www.linear.com/ltc3886 p m b us c o mm an d s u mm ary command name cmd code description type paged d ata format units eeprom default value page vout_margin_low 0x26 margin low output voltage set point. must be less than vout_command. r/w word y l16 v y 0.95 0x0f33 79 vout_transition_ rate 0x27 rate the output changes when vout commanded to a new value. r/w word y l11 v/ms y 0.25 0xaa00 85 frequency_switch 0x33 switching frequency of the controller. r/w word n l11 khz y 350 0xfabc 76 vin_on 0x35 input voltage at which the unit should start power conversion. r/w word n l11 v y 6.5 0xcb40 77 vin_off 0x36 input voltage at which the unit should stop power conversion. r/w word n l11 v y 6.0 0xcb00 77 iout_cal_gain 0x38 the ratio of the voltage at the current sense pins to the sensed current. for devices using a fixed current sense resistor, it is the resistance value in m. r/w word y l11 m y 1.8 0xbb9a 80 vout_ov_fault_limit 0x40 output overvoltage fault limit. r/w word y l16 v y 1.1 0x119a 78 vout_ov_fault_ response 0x41 action to be taken by the device when an output overvoltage fault is detected. r/w byte y reg y 0xb8 87 vout_ov_warn_limit 0x42 output overvoltage warning limit. r/w word y l16 v y 1.075 0x1133 78 vout_uv_warn_limit 0x43 output undervoltage warning limit. r/w word y l16 v y 0.925 0x0ecd 79 vout_uv_fault_limit 0x44 output undervoltage fault limit. r/w word y l16 v y 0.9 0x0e66 79 vout_uv_fault_ response 0x45 action to be taken by the device when an output undervoltage fault is detected. r/w byte y reg y 0xb8 88 iout_oc_fault_limit 0x46 output overcurrent fault limit. r/w word y l11 a y 29.75 0xdbb8 81 iout_oc_fault_ response 0x47 action to be taken by the device when an output overcurrent fault is detected. r/w byte y reg y 0x00 90 iout_oc_warn_limit 0x4a output overcurrent warning limit. r/w word y l11 a y 20.0 0xda80 82 ot_fault_limit 0x4f external overtemperature fault limit. r/w word y l11 c y 100.0 0xeb20 83 ot_fault_response 0x50 action to be taken by the device when an external overtemperature fault is detected, r/w byte y reg y 0xb8 92 ot_warn_limit 0x51 external overtemperature warning limit. r/w word y l11 c y 85.0 0xeaa8 83 ut_fault_limit 0x53 external undertemperature fault limit. r/w word y l11 c y C40.0 0xe580 84 ut_fault_response 0x54 action to be taken by the device when an external undertemperature fault is detected. r/w byte y reg y 0xb8 92 vin_ov_fault_limit 0x55 input supply overvoltage fault limit. r/w word n l11 v y 48.0 0xe300 76 vin_ov_fault_ response 0x56 action to be taken by the device when an input overvoltage fault is detected. r/w byte y reg y 0x80 87 vin_uv_warn_limit 0x58 input supply undervoltage warning limit. r/w word n l11 v y 6.3 0xcb26 77 iin_oc_warn_limit 0x5d input supply overcurrent warning limit. r/w word n l11 a y 10.0 0xd280 82 ltc 3886 3886f 37 for more information www.linear.com/ltc3886 p m b us c o mm an d s u mm ary command name cmd code description type paged d ata format units eeprom default value page ton_delay 0x60 time from run and/or operation on to output rail turn-on. r/w word y l11 ms y 0.0 0x8000 84 ton_rise 0x61 time from when the output starts to rise until the output voltage reaches the vout commanded value. r/w word y l11 ms y 8.0 0xd200 84 ton_max_fault_limit 0x62 maximum time from the start of ton_rise for vout to cross the vout_uv_fault_limit. r/w word y l11 ms y 10.00 0xd280 85 ton_max_fault_ response 0x63 action to be taken by the device when a ton_ max_fault event is detected. r/w byte y reg y 0xb8 90 toff_delay 0x64 time from run and/or operation off to the start of toff_fall ramp. r/w word y l11 ms y 0.0 0x8000 85 toff_fall 0x65 time from when the output starts to fall until the output reaches zero volts. r/w word y l11 ms y 8.00 0xd200 85 toff_max_warn_ limit 0x66 maximum allowed time, after toff_fall completed, for the unit to decay below 12.5%. r/w word y l11 ms y 150.0 0xf258 86 status_byte 0x78 one byte summary of the units fault condition. r/w byte y reg na 98 status_word 0x79 tw o byte summary of the units fault condition. r/w word y reg na 98 status_vout 0x7a output voltage fault and warning status. r/w byte y reg na 99 status_iout 0x7b output current fault and warning status. r/w byte y reg na 100 status_input 0x7c input supply fault and warning status. r/w byte n reg na 100 status_temperature 0x7d external temperature fault and warning status for read_temerature_1. r/w byte y reg na 101 status_cml 0x7e communication and memory fault and warning status. r/w byte n reg na 101 status_mfr_specific 0x80 manufacturer specific fault and state information. r/w byte y reg na 102 read_vin 0x88 measured input supply voltage. r word n l11 v na 104 read_iin 0x89 measured input supply current. r word n l11 a na 104 read_vout 0x8b measured output voltage. r word y l16 v na 104 read_iout 0x8c measured output current. r word y l11 a na 104 read_temperature_1 0x8d external temperature sensor temperature. this is the value used for all temperature related processing, including iout_cal_gain. r word y l11 c na 104 read_temperature_2 0x8e internal die junction temperature. does not affect any other commands. r word n l11 c na 104 read_frequency 0x95 measured pwm switching frequency. r word y l11 hz na 104 read_pout 0x96 calculated output power. r word y l11 w na 105 read_pin 0x97 calculated input power r word n l11 w na 105 pmbus_revision 0x98 pmbus revision supported by this device. current revision is 1.2. r byte n reg 0x22 96 mfr_id 0x99 the manufacturer id of the ltc3886 in ascii. r string n asc lt c 96 mfr_model 0x9a manufacturer part number in ascii. r string n asc ltc3886 96 mfr_vout_max 0xa5 maximum allowed output voltage including vout_ov_fault_limit. r word y l16 v 14.0 0xe000 80 ltc 3886 3886f 38 for more information www.linear.com/ltc3886 p m b us c o mm an d s u mm ary command name cmd code description type paged d ata format units eeprom default value page user_data_00 0xb0 oem reserved. typically used for part serialization. r/w word n reg y na 96 user_data_01 0xb1 manufacturer reserved for ltpowerplay. r/w word y reg y na 96 user_data_02 0xb2 oem reserved. typically used for part serialization r/w word n reg y na 96 user_data_03 0xb3 an eeprom word available for the user. r/w word y reg y 0x0000 96 user_data_04 0xb4 an eeprom word available for the user. r/w word n reg y 0x0000 96 mfr_ee_unlock 0xbd contact factory. 111 mfr_ee_erase 0xbe contact factory. 111 mfr_ee_ data 0xbf contact factory. 111 mfr_chan_config_ lt c 3886 0xd0 configuration bits that are channel specific. r/w byte y reg y 0x1d 70 mfr_config_all_ lt c 3886 0xd1 general configuration bits. r/w byte n reg y 0x21 70 mfr_fault_ propagate_ lt c 3886 0xd2 configuration that determines which faults are propagated to the fault pin. r/w word y reg y 0x6993 93 mfr_pwm_comp 0xd3 pwm loop compensation configuration r/w byte y reg y 0x70 73 mfr_pwm_mode_ lt c 3886 0xd4 configuration for the pwm engine. r/w byte y reg y 0xc1 72 mfr_fault_response 0xd5 action to be taken by the device when the fault pin is externally asserted low. r/w byte y reg y 0xc0 95 mfr_ot_fault_ response 0xd6 action to be taken by the device when an internal overtemperature fault is detected. r byte n reg 0xc0 91 mfr_iout_peak 0xd7 report the maximum measured value of read_iout since last mfr_clear_peaks. r word y l11 a na 105 mfr_adc_control 0xd8 adc telemetry parameter selected for repeated fast adc read back r/w byte n reg 0x00 108 mfr_retry_delay 0xdb retry interval during fault retry mode. r/w word y l11 ms y 350.0 0xfabc 86 mfr_restart_delay 0xdc minimum time the run pin is held low by the ltc3886. r/w word y l11 ms y 500.0 0xfbe8 86 mfr_vout_peak 0xdd maximum measured value of read_vout since last mfr_clear_peaks. r word y l16 v na 105 mfr_vin_peak 0xde maximum measured value of read_vin since last mfr_clear_peaks. r word n l11 v na 105 mfr_temperature_1_ peak 0xdf maximum measured value of external temperature (read_temperature_1) since last mfr_clear_peaks. r word y l11 c na 105 mfr_read_iin_peak 0xe1 maximum measured value of read_iin command since last mfr_clear_peaks r word n l11 a na 105 mfr_clear_peaks 0xe3 clears all peak values. send byte n na 98 mfr_read_ichip 0xe4 measured supply current of the ltc3886 r word n l11 a na 106 mfr_pads 0xe5 digital status of the i/o pads. r word n reg na 102 mfr_address 0xe6 sets the 7-bit i 2 c address byte. r/w byte n reg y 0x4f 69 mfr_special_id 0xe7 manufacturer code representing the ltc3886 and revision r word n reg 0x460x 96 ltc 3886 3886f 39 for more information www.linear.com/ltc3886 p m b us c o mm an d s u mm ary command name cmd code description type paged d ata format units eeprom default value page mfr_iin_cal_gain 0xe8 the resistance value of the input current sense element in m. r/w word n l11 m y 5.0 0xca80 82 mfr_fault_log_ store 0xea command a transfer of the fault log from ram to eeprom. send byte n na 108 mfr_fault_log_ clear 0xec initialize the eeprom block reserved for fault logging. send byte n na 111 mfr_fault_log 0xee fault log data bytes. r block n reg y na 108 mfr_common 0xef manufacturer status bits that are common across multiple lt c chips. r byte n reg na 103 mfr_compare_user_ all 0xf0 compares current command contents with eeprom. send byte n na 107 mfr_temperature_2_ peak 0xf4 peak internal die temperature since last mfr_ clear_peaks. r word n l11 c na 106 mfr_pwm_config_ lt c 3886 0xf5 set numerous parameters for the dc/dc controller including phasing. r/w byte n reg y 0x10 75 mfr_iout_cal_gain_ tc 0xf6 temperature coefficient of the current sensing element. r/w word y cf ppm/ ?c y 3900 0x0f3c 80 mfr_rvin 0xf7 the resistance value of the v in pin filter element in m. r/w word n l11 m y 2000 0x0be8 77 mfr_temp_1_gain 0xf8 sets the slope of the external temperature sensor. r/w word y cf y 1.0 0x4000 83 mfr_temp_1_offset 0xf9 sets the offset of the external temperature sensor with respect to C273.1c r/w word y l11 c y 0.0 0x8000 83 mfr_rail_address 0 xfa common address for polyphase outputs to adjust common parameters. r/w byte y reg y 0x80 69 mfr_reset 0xfd commanded reset without requiring a power down. send byte n na 72 note 1: commands indicated with y in the eeprom column indicate that these commands are stored and restored using the store_user_all and restore_user_all commands, respectively. note 2: commands with a default value of na indicate not applicable. commands with a default value of fs indicate factory set on a per part basis. note 3: the ltc3886 contains additional commands not listed in this table. reading these commands is harmless to the operation of the ic; however, the contents and meaning of these commands can change without notice. note 4: some of the unpublished commands are read-only and will generate a cml bit 6 fault if written. note 5: writing to commands not published in this table is not permitted. note 6: the user should not assume compatibility of commands between different parts based upon command names. always refer to the manufacturers data sheet for each part for a complete definition of a commands function. lt c strives to keep command functionality compatible between all lt c devices. differences may occur to address specific product requirements. ltc 3886 3886f 40 for more information www.linear.com/ltc3886 p m b us c o mm an d s u mm ary *d ata f ormat l11 linear_5s_11s pmbus data field b[15:0] value = y ? 2 n where n = b[15:11] is a 5-bit twos complement integer and y = b[10:0] is an 11-bit twos complement integer example: for b[15:0] = 0x9807 = b10011_000_0000_0111 value = 7 ? 2 C13 = 854 ? 10 C6 from pmbus spec part ii: paragraph 7.1 l16 linear_16u pmbus data field b[15:0] value = y ? 2 n where y = b[15:0] is an unsigned integer and n = vout_mode_parameter is a 5-bit twos complement exponent that is hardwired to C12 decimal example: for b[15:0] = 0x9800 = b1001_1000_0000_0000 value = 38912 ? 2 C12 = 9.50 from pmbus spec part ii: paragraph 8.2 reg register pmbus data field b[15:0] or b[7:0]. bit field meaning is defined in detailed pmbus command description. i16 integer word pmbus data field b[15:0] value = y where y = b[15:0] is a 16-bit unsigned integer example: for b[15:0] = 0x9807 = b1001_1000_0000_0111 value = 38919 (decimal) cf custom format v alue is defined in detailed pmbus command description. this is often an unsigned or twos complement integer scaled by an mfr specific constant. asc ascii format a variable length string of text characters conforming to iso/iec 8859-1 standard. ltc 3886 3886f 41 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion the typical application on the last page of this data sheet is a common ltc3886 application circuit. the ltc3886 can be configured to use either dcr ( inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade- off between cost, power consumption and accuracy. dcr sensing is popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. the ltc3886 can nominally account for the temperature dependency of the dcr sensing element. the accuracy of the current reading and current limit are typically limited by the accuracy of the dcr of the inductor ( which is programmed as the iout_ cal_ gain register of the ltc3886). however , current sensing resistors provide the most accurate current sense and limiting. other external component selections are driven by the load requirement, and begins with the selection of r sense ( if r sense is used) and inductor value. next, the power mosfets are selected. then the input and output capacitors are selected. finally the current limit is selected. all of these components and ranges are required to be determined prior to selecting the rith and ea_gm values in the mfr_pwm_comp register and calculating the external compensation components. the current limit range is required because the two ranges (25 mv to 50mv vs 37.5 mv to 75 mv) have different ea gains set with bit 7 of the mfr_pwm_mode_ltc3886 command. the voltage range bit also affects the loop gain and impacts the compensation network. the voltage range is set with bit 1 of mfr_pwm_mode_ lt c 3886. all other program - mable parameters do not affect the loop gain, allowing parameters to be modified without impacting the transient response to load changes. c urrent l imit p rogramming the ltc3886 has two ranges of current limit programming and a total of eight levels within each range. refer to the iout_ oc_ fault_ limit section of the pmbus commands. within each range the error amp gain is fixed, resulting in constant loop gain. the ltc3886 will account for the temperature coefficient of the inductor dcr and automatically adjust the current limit when indutor temperature changes. the temperature coefficient of the dcr is stored in the mfr_ iout_ cal_ gain_ tc command. for the best current limit accuracy, use the 75 mv setting. the 25 mv setting will allow for the use of very low dcr inductors or sense resistors, but at the expense of current limit accuracy. peak current limiting is on a cycle-by-cycle basis. the average inductor current is monitored by the adc converter and can provide a warning if too much average output current is detected. an overcurrent fault is detected when the i th voltage exceeds the limit set by iout_oc_fault_limit. the digital processor within the ltc3886 provides the ability to either ignore the fault, shut down and latch off or shut down and retry indefinitely (retry). refer to the overcurrent portion of the operation section for more detail. i sense + and i sense C p ins the i sense + and i sense C pins are the inputs to the current comparator and the a/d. the common mode input voltage range of the current comparators is 0 v to 14 v. both the sense pins are high impedance inputs with small input currents typically less than 1 a. the high impedance inputs to the current comparators enable accurate dcr sensing. do not float these pins during normal operation. filter components connected to the i sense traces should be placed close to the ic. the positive and negative traces should be routed differentially and kelvin connected to the current sense element, see figure 24. a non-kelvin connection or improper placement can add parasitic in - ductance and capacitance to the current sense element, degrading the signal at the sense terminals and making the programmed current limit perform poorly. in a polyphase system, poor placement of the sensing element will result in sub-optimal current sharing between power stages. if dcr sensing is used ( figure 25a ), sense resistor r 1 should be placed close to the inductor to prevent noise from coupling into sensitive small-signal nodes. the capacitor c1 should be placed close to the ic pins. any impedance c out to sense filter, next to the controller inductor or r sense 3886 f24 figure 24. optimal sense line placement ltc 3886 3886f 42 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion difference between the i sense + and i sense C signal paths can result in loss of accuracy in the current reading of the adc. the current reading accuracy can be improved by matching the impedance of the two signal paths. to accomplish this add a series resistor between v out and i sense C equal to r1. a capacitor of 1 f or greater should be placed in parallel with this resistor. if the peak voltage is <75mv at room temperature, r2 is not required. l ow v alue r esistor c urrent s ensing a typical sensing circuit using a discrete resistor is shown in figure 25 b. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) determined by the i limit setting. the input common mode range of the current comparator is 0 v to 14v ( if v in is greater than 15 v). the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current ?i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + ? i l 2 due to possible pcb noise in the current sensing loop, the ac current sensing ripple of ?v sense = ?i l ? r sense also needs to be checked in the design to get a good signal-to- noise ratio. in general, for a reasonably good pcb layout, a 15 mv minimum ?v sense voltage is recommended as a conservative number to start with, either for r sense or dcr sensing applications. for previous generation current mode controllers, the maximum sense voltage was high enough ( e.g ., 75mv for the ltc1628/ ltc3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. in the newer and higher current density solutions, the value of the sense resistor can be less than 1 m and the peak sense voltage can be less than 20mv. also, inductor ripple currents greater than 50% with operation up to 750khz are becoming more common. under these conditions, the voltage drop across the sense resistor s parasitic inductance is no longer negligible. a typical sensing circuit using a discrete resistor is shown in figure 25b . in previous generations of controllers, a small rc filter placed near the ic was commonly used to reduce the effects of the capacitive and inductive noise coupled in the sense traces on the pcb. a typical filter consists of two series 100 resistors connected to a parallel 1000pf capacitor, resulting in a time constant of 200ns. v in v in intv cc boost tg sw bg gnd *place c1 near sense + , sense ? pins inductor dcr r3 optional c2 >1f l i sense + i sense ? ltc3886 v out 3886 f25a r1 r2c1* ((r1+ r3)||r2) c1 = 2 l dcr iout_cal_gain = dcr r2 r1 + r2 + r3 r3 = r1 v in v in intv cc boost tg sw bg gnd filter components placed near sense pins i sense + i sense ? ltc3886 v out 3886 f25b c f ? 2 rf esl/r s pole-zero cancellation sense resistor plus parasitic inductance r s esl c f r f r f figure 25a. inductor dcr current sense circuit figure 25b. resistor current sense circuit ltc 3886 3886f 43 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion this same rc filter with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. for example, figure 26 illustrates the voltage waveform across a 2m resistor with a pcb footprint of 2010. the waveform is the superposition of a purely resistive component and a purely inductive component. it was measured using two scope probes and waveform math to obtain a differential measurement. based on additional measurements of the inductor ripple current and the on-time, t on , and off-time, t off , of the top switch, the value of the parasitic inductance was determined to be 0.5nh using the equation: esl = v esl(step) ? i l ? t on ? t off t on + t off (1) if the rc time constant is chosen to be close to the para - sitic inductance divided by the sense resistor ( l/r), the resultant waveform looks resistive, as shown in figure 27. for applications using low maximum sense voltages, check the sense resistor manufacturers data sheet for information about parasitic inductance. in the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the esl step and use equation 1 to determine the esl. however, do not overfilter the signal. keep the rc time constant less than or equal to the inductor time constant to maintain a sufficient ripple voltage on v rsense for optimal operation of the current loop controller. i nductor dcr c urrent s ensing for applications requiring the highest possible efficiency at high load currents, the ltc3886 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 25 a. the dcr of the inductor represents the small amount of dc winding resistance of the copper, which can be less than 1 m for todays low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor would reduce the efficiency by a few percent compared to dcr sensing. if r 1 = r3 and the external (r1 + r3)||r 2 ? c1 time constant is chosen to be exactly equal to the 2 ? l/dcr time constant, assuming r 1 = r3, the voltage drop across the external capacitor,c1, is equal to the drop across the inductor dcr multiplied by r2/(r 1 + r2 + r3). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. the dcr value is entered as the iout_cal_gain in m unless r2 is required. if r2 is used: iout _cal _gain = dcr ? r2 r1 + r2 + r3 r2 can be removed if there is no need to attenuate the current sense signal in order to remain within the desired current sense range. to properly select the external filter components, the dcr of the inductor must be known. it can be measured using an accurate rlc meter, but the dcr tolerance is not always the same and varies with temperature. consult the inductor manufacturers data sheets for detailed information. the ltc3886 will correct for temperature variation if the correct temperature coefficient value is entered into the mfr_ iout_ cal_ gain_ tc command. typically the resistance has a 3900ppm/c coefficient. 500ns/div v sense 20mv/div 3886 f26 v esl(step) 500ns/div v sense 20mv/div 3886 f27 figure 26. voltage measured directly across r sense figure 27. voltage measured after the r sense filter ltc 3886 3886f 44 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion assuming r 1 = r 3, c 2 can be optimized for a flat frequency response using the following equation: c2 = 2r1 ? r2 ? c1C l dcr 2r1 + r2 ( ) r1 2 using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: r sense(equiv) = v sense(max) i max + ? i l 2 to ensure that the application will deliver full load current over the full operating temperature range, be sure to pick the optimum i limit value accounting for tolerance in the dcr versus the mfr _ iout _ cal_ gain parameter entered . next, determine the dcr of the inductor. use the manu - facturers maximum value, which is usually specified at 20c. increase this value to account for tolerances in the temperature sensing element of 3 c to 5 c and any addi - tional temperature differences associated with the proximity of the temperature sensor element to the inductor. c1 is usually selected to be in the range of 0.047 f to 4.7f. this forces (r1 + r3)||r2 to be approximately 2k. adding optional elements r3 and c2 shown in figure 18a will minimize offset errors associated with the i sense leak- age currents. set r3 equal to the value of r1. set c2 to a value of 1 f or greater to ensure adequate noise filtering. the equivalent resistance (r1 + r3)||r2 is scaled to the room temperature inductance and maximum dcr: r1 + r3 ( ) ||r2 = l 2 ? dcr at 20 c ( ) ? c1 the maximum power loss in r1 is related to the duty cycle, and will occur in continuous mode at the maximum input voltage: p loss r1 = v in(max) ? v out ( ) ? v out r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduc - ing conduction losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. selecting discontinuous mode will improve the converter efficiency at light loads regardless of the current sensing method. to maintain a good signal-to-noise ratio for the current sense signal, use a minimum ?v isense of 10 mv to 15mv. for a dcr sensing application, the actual ripple voltage will be determined by the equation: ? v isense = v in ? v out r1 ? c1 ? v out v in ? f osc s lope c ompensation and i nductor p eak c urrent slope compensation provides stability in constant fre - quency current mode ar chitectures by preventing sub- harmonic oscillations at high duty cycles. this is accom- plished internally by adding a compensation ramp to the inductor current signal at duty cycles in excess of 35%. the ltc3886 uses a patented current limit technique that cancels the effect of the compensating ramp. this allows the maximum inductor peak current to remain unaffected throughout all duty cycles. i nductor v alue c alculation given the desired input and output voltages, the inductor value and operating frequency, f osc , directly determine the inductor peak-to-peak ripple current: i ripple = v out v in ? v out ( ) v in ? f osc ? l lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest efficiency operation is obtained at the lowest frequency with a small ripple current. achieving this, however, requires a large inductor. ltc 3886 3886f 45 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that the ripple current does not exceed a specified maxi - mum, the inductor should be chosen according to: l v out v in ? v out ( ) v in ? f osc ? i ripple i nductor c ore s election once the inductor value is determined, the type of induc- tor must be selected. core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance. as the inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. ferrite core materials saturate hard, which means that the induc- tance collapse abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! p ower mosfet and o ptional s chottky d iode s election two external power mosfets must be selected for each output channel in the ltc3886: one n-channel mosfet for the top ( main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak gate drive levels are set by the intv cc voltage. this voltage is typically 5 v. consequently, logic- level threshold mosfets must be used in most applica - tions. the only exception is if low input voltage is expected (v in < 5 v); then, sub-logic level threshold mosfets (v gs(th) < 3 v) should be used. pay close attention to the bv dss specification for the mosfets as well; most of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance, r ds(on) , miller capacitance, c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in ? v out v in the mosfet power dissipations at maximum output current are given by: p main = v out v in i max ( ) 2 1 + d ( ) r ds(on) + v in ( ) 2 i max 2 ? ? ? ? ? ? r dr ( ) c miller ( ) ? 1 v intvcc ? v th(min) + 1 v th(min) ? ? ? ? ? ? ? ? ? f osc p sync = v in ? v out v in i max ( ) 2 1 + d ( ) r ds(on) where d is the temperature dependency of r ds(on) and r dr (approximately 2?) is the effective driver resistance at the mosfets miller threshold voltage. v th(min) is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n- channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20 v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during ltc 3886 3886f 46 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. the optional schottky diodes connected from ground to swn conduct during the dead time between the conduction of the two power mosfets. these prevent the body diodes of the bottom mosfets from turning on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high v in . a 1 a to 3 a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. c in and c out s election in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in ? v out ( ) ? ? ? ? 1/2 this formula has a maximum at v in = 2 ? v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capaci - tor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3886, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the benefit of using a ltc3886 in 2- phase operation can be calculated by using the equation above for the higher power channel and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both channels are operating due to the reduced overlap of current pulses required through the input capacitor s esr. this is why the input capacitors requirement calculated above for the worst-case scenario is adequate for the dual controller design. also, if applicable the power losses due to the input protection fuse resistance, v in source impedance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. the overall benefit of a multiphase design will only be fully realized when the source impedance of the v in power supply/battery is included in the efficiency testing. the drain terminals of the top mosfets should be placed within 1 cm of each other and share a common c in (s). separating the sources and c in may produce undesirable voltage and current resonances on v in . a small (0.1 f to 1 f) bypass capacitor between the chip v in pin and ground, placed close to the ltc3886, is also suggested. a 2.2? to 10? r vin resistor placed between c in ( c1) and the v in pin provides further isolation if mul- tiple ltc3886s are used. the selection of c out is driven by the effective series resistance ( esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple (?v out ) is approximated by: ? v out i ripple esr + 1 8fc out ? ? ? ? ? ? where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the inductor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. v ariable d elay t ime , s oft -s tart and o utput v oltage r amping the ltc3886 must enter the run state prior to soft-start. the run n pin is released after the part initializes and v in is greater than the vin _ on threshold. if multiple ltc3886 s are used in an application, they should be configured to share the same run n pins. they all hold their respective runn pins low until all devices initialize and v in exceeds the vin_on threshold for all devices. the share_clk ltc 3886 3886f 47 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion pin assures all the devices connected to the signal use the same time base for time delay operations. after the run n pin releases, the controller waits for the user-specified turn-on delay ( ton_delay) prior to initiating an output voltage ramp. multiple ltc3886s and other ltc parts can be configured to start with equal or unique delay times. to work within a desired synchronization scheme all devices must use the same timing clock ( share_clk) and all devices must share the run n pin. this allows the relative delay of all parts to be synchronized. the actual variation in the delays will be dependent on the highest clock rate of the devices connected to the share_clk pin ( all linear technology ics are configured to allow the fastest share_clk signal to control the timing of all devices). the share_ clk signal can be 10% in frequency, thus the actual time delays will have proportional variance. soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0.0v to the commanded voltage set point. the rise time of the voltage ramp can be programmed using the ton_rise command to minimize inrush currents associated with the start-up voltage ramp. the soft-start feature is disabled by setting ton_rise to any value less than 0.250 ms. the ltc3886 will perform the necessary math to assure the voltage ramp is controlled to the desired slope. however, the voltage slope can not be any faster than the fundamental limits of the power stage. the shorter ton_rise time is set, the larger the descrete steps in the ton_rise ramp will appear. the number of steps in the ramp is equal to ton_rise/0.1ms. the ltc3886 pwm will always use discontinuous mode during the ton_rise operation. in discontinuous mode, the bottom gate is turned off as soon as reverse current is detected in the inductor. this will allow the regulator to start up into a pre-biased load. the ltc3886 does not include a traditional tracking feature. however, two outputs can be given the same ton_rise and ton_delay times to effectively ramp up at the same time. if the run pin is released at the same time and both ltc3886s use the same time base, the outputs will track very closely. if the circuit is in a polyphase configuration, all timing parameters for that rail must be the same. the previously described method of start-up sequencing is time based. for concatenated events it is possible to control the run n pins based on the faultn pin of a different controller, or the pgoodn pin(s) of the ltc3886. the faultn pins can be configured to release when the output voltage of the converter is greater than the vout_ uv _ fault _ limit. it is recommended to use the deglitched v out uv fault limit because there is little appreciable time delay between the converter crossing the uv threshold and the faultn pin releasing. the deglitched output can be enabled by setting the mfr_fault_propagate_vout_uvuf bit in the mfr_ fault_ propagate_ ltc3886 command . refer to the mfr section of the pmbus commands in this document. the uv comparator output signal may have some glitching as the v out signal transitions through the comparator threshold. the ltc3886 includes a 250s digital deglitch filter to greatly reduce the probability of multiple transitions. to minimize the risk of faultn pins glitching, make the ton_rise times less than 100ms. if unwanted transitions still occur on fault n , place a capaci- tor to ground on the faul t n pin to filter the waveform. the rc time-constant of the filter should be set sufficiently fast to assure no appreciable delay is incurred. a delay of 300 s to 500 s will provide some additional filtering without significantly delaying the trigger event. d igital s ervo m ode for maximum accuracy in the regulated output voltage, enable the digital servo loop by asserting bit 6 of the mfr_pwm_mode_ltc3886 command . in digital servo mode the ltc3886 will adjust the regulated output voltage based on the adc voltage reading. every 100ms the digital servo loop will step the lsb of the dac ( nominally 4 mv or 2mv depending on the voltage range bit) until the output is at the correct adc reading. at power-up this mode engages after ton_max_fault_limit unless the limit is set to 0 ( infinite). if the ton_max_fault_limit is set to ?0 ( infinite), the servo begins after ton _ rise is complete and v out has exceeded the vout_uv_fault_limit. this same point in time is when the output changes from discontinuous to the programmed mode as indicated in mfr_pwm_mode_ lt c 3886 bit 0. refer to figure? 28 for details on the v out waveform under time-based sequencing. ltc 3886 3886f 48 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion if the ton_max_fault_limit is set to a value greater than 0 and the ton_max_fault_response is set to ignore (0x00), the servo begins: 1. after the ton_rise sequence is complete 2. after the ton_max_fault_limit time is reached. 3. after the vout_uv_fault_limit has been exceed or the iout_oc_fault_limit is not longer active. if the ton_max_fault_limit is set to a value greater than 0 and the ton_max_fault_response is not set to ignore 0x00, the servo begins: 1. after the ton_rise sequence is complete; 2. after the ton_max_fault_limit time has expired and both vout_uv_fault and iout_oc_fault are not present. the maximum rise time is limited to 1.3 seconds. in a polyphase application only one phase should have digital servo mode enabled. this will ensure the phases servo to the same output regulation point. s oft o ff (s equenced o ff ) in addition to a controlled start- up, the ltc3886 also supports controlled turn- off. the toff_ delay and toff_ fall functions are shown in figure 29. toff_ fall is processed when the run pin goes low or if the part is commanded off. if the part faults off or fault n is pulled low externally and the part is programmed to respond to fault n , the output will three- state by turning off both the main and synchronous mosfets turned off. the output will decay as a function of the load rather than exhibiting a controlled ramp. the output voltage will ramp as shown in figure 29 so long as the part is in forced continuous mode and the toff_fall time is slow enough that the power stage can achieve the desired slope. the toff_fall time can only be met if the power stage and controller can sink sufficient current to assure the output is at zero volts by the end of the fall time interval. if the toff_fall time is set shorter than the time required to discharge the load capacitance, the output will not reach the desired zero volt state. at the end of toff_fall, the controller will cease to sink current and v out will decay at the natural rate determined by the load impedance. if the controller is in discontinuous mode, the controller will not pull negative current and the output will be pulled low by the load, not the power stage. the maximum fall time is limited to 1.3 seconds. the shorter toff_fall time is set, the larger the discrete steps of the toff_fall ramp will appear. the number of steps in the ramp is typically toff_fall/0.1ms. intv cc r egulator the ltc3886 features a pmos linear regulator that sup- plies power to intv cc from the v in or extv cc supply. intv cc powers the gate drivers, v dd33 and much of the ltc3886 internal circuitry. the linear regulator produces 5v at the intv cc pin when v in or extv cc is greater than approximately 5.5 v. the regulator can supply a peak cur- rent of 100ma and must be bypassed to ground with a dac voltage error (not to scale) time delay of 200-400ms digital servo mode enabled final output voltage reached ton_max_fault_limit ton_rise time 3886 f28 ton_delay v out figure 28. timing controlled v out rise toff_fall toff_delay time 3886 f29 v out figure 29. toff_delay and toff_fall ltc 3886 3886f 49 for more information www.linear.com/ltc3886 r vin 1 c in 3886 f30 5v c intvcc 4.7f + intv cc /extv cc ltc3886 v in figure 30. setup for a 5v input a pplica t ions i n f or m a t ion minimum of 1 f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capacitor is used, an additional 0.1 f ceramic capacitor placed directly adjacent to the intv cc and gnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers. h igh input voltage application in which large mosfets are being driven at high frequencies may cause the maximum die junction temperature rating for the ltc3886 to be exceeded. to reduce die temperature, the intv cc current, of which a large percentage is due to the gate charge current, may be supplied from either the v in or extv cc pin. if the ltc3886 internal regula- tor is powered from the v in pin , the power through the ic is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. the junction tempera- ture can be estimated by using the equations in note 2 of the electrical characteristics. for example, at 70 c ambient, the ltc3886 intv cc current is limited to less than 44ma from a 40v supply: t j = 70c + 44ma ? 40v ? 31c/w = 125c to prevent the maximum junction temperature from being exceeded, the ltc3886 internal ldo can be can powered from the extv cc pin. if the extv cc pin is not used to power intv cc , the extv cc pin must be tied to gnd, do not float this pin. the v in current resulting from the gate driver and control circuitry will be reduced to a minimum by supplying the intv cc current from the extv cc pin with an external supply or an output derived source. tying the extv cc pin to a 5 v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + 44ma ? 5 v ? 31c/w + 2ma ? 40 v ? 31c/w = 80c do not tie intv cc on the ltc3886 to an external supply because intv cc will attempt to pull the external supply high and hit current limit, significantly increasing the die temperature. for applications where v in is 5 v, tie the v in and intv cc pins together and tie the combined pins to the 5 v input with a 1 or 2.2 resistor as shown in figure 30. to minimize the voltage drop caused by the gate charge current a low esr capacitor must be connected to the v in /intv cc pins. this configuration will override the intv cc linear regula- tor and will prevent intv cc from dropping too low. make sure the intv cc voltage exceeds the r ds(on) test voltage for the mosfets which is typically 4.5 v for logic level devices. the uvlo on intv cc is set to approximately 4v. t opside mosfet d river s upply (c b , d b ) external bootstrap capacitors, c b , connected to the boostn pin supplies the gate drive voltages for the topside mosfets. capacitor c b in the block diagram is charged though external diode d b from intv cc when the sw n pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw n , rises to v in and the boost n pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) . pwm jitter has been observed on the tg and bg pins in some designs operating at higher v in /v out ratios. this jitter does not substantially affect the circuit output volt- age accuracy . referring to figure 31, pwm jitter can be removed by inserting a series resistor with a value of 1 to 5 between the cathode of the diode and the boost n pin. ltc 3886 3886f 50 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion u ndervoltage l ockout the ltc3886 is initialized by an internal threshold-based uvlo where v in must be approximately 4 v and intv cc , v dd33 , v dd25 must be within approximately 20% of the regulated values. in addition, v dd33 must be within approximately 7% of the targeted value before the run pin is released. after the part has initialized, an additional comparator monitors v in . the vin_on threshold must be exceeded before the power sequencing can begin. when v in drops below the vin_off threshold, the share_clk pin will be pulled low and v in must increase above the vin_on threshold before the controller will restart. the normal start-up sequence will be allowed after the vin_on threshold is crossed. if fault n is held low when v in is applied, alert will be asserted low even if the part is programmed to not assert alert when fault n is held low. if i 2 c communication occurs before the ltc3886 is out of reset and only a portion of the command is seen by the part, this can be interpreted as a cml fault . if a cml fault is detected, alert is asserted low. it is possible to program the contents of the eeprom in the application if the v dd33 supply is externally driven. this will activate the digital portion of the ltc3886 without engaging the high voltage sections. pmbus communications are valid in this supply configuration. if v in has not been applied to the ltc3886, bit 3 ( eeprom not initialized)in mfr_common will be asserted low. if this condition is detected, the part will only respond to addresses 5 a and 5 b. to initialize the part issue the following set of commands: global address 0 x5b command 0 xbd data 0 x2b followed by global address 5 b command 0 xbd and data 0 xc4. the part will now respond to the correct address. configure the part as desired then issue a store_user_all. when v in is applied a mfr_reset command must be issued to allow the pwm to be enabled and valid adc conversions to be read. f ault i ndications the ltc3886 faul tn pins are configurable to indicate a variety of faults including ov, uv, oc, ot, timing faults, peak overcurrent faults. in addition the fault n pins can be pulled low by external sources indicating a fault in some other portion of the system. the fault response is configurable and allows the following options: n ignore n shut down immediatelylatch off n shut down immediatelyretry indefinitely at the time interval specified in mfr_retry_delay refer to the pmbus section of the data sheet and the pmbus specification for more details regarding fault responses. the ov response is always automatic. if an ov condition is detected, tgn goes low and bgn is asserted. o pen -d rain p ins the ltc3886 has the following open-drain pins: 3.3v pins 1. fault n 2. sync 3. share_clk 4. pgoodn 5v pins (5 v pins operate correctly when pulled to 3.3v.) 1. runn 2. alert 3. scl 4. sda v in tgate ltc3886 sw d b intv cc boost c b 0.2f 1 to 5 v in c intvcc 10f 3886 f31 bgate gnd figure 31. boost circuit to minimize pwm jitter ltc 3886 3886f 51 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion all the above pins have on-chip pull-down transistors that can sink 3 ma at 0.4 v. the input low threshold on the pins is 1.4 v. unless there are transient speed issues associ - ated with the rc time constant of the resistor pull-up and parasitic capacitance to ground, a 10 k resistor or larger is generally recommended. for high speed signals such as the sda, scl and sync, a lower value resistor may be required. the rc time con - stant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. for a 100 pf load and a 400khz pmbus communication rate, the rise time must be less than 300 ns. the resistor pull-up on the sda and scl pins with the time constant set to 1/3 the rise time: r pullup = t rise 3 ? 100pf = 1k minimize parasitic capacitance on the sda and scl pins to avoid communication problems. to estimate the loading capacitance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. this is one time constant. the sync pin has an on-chip pull-down transistor with the output held low for nominally 500 ns. if the internal oscillator is set for 500 khz and the load is 100 pf and a 3x time constant is required, the resistor calculation is as follows: r pullup = 2s ? 500ns 3 ? 100pf = 5k if timing errors are occurring or if the sync frequency is not as fast as desired, monitor the waveform and determine if the rc time constant is too long for the application. if possible reduce the parasitic capacitance. if not reduce the pull up resistor sufficiently to assure proper timing. the share_clk pull-up resistor has a similar equation with a period of 10 us and a pull-down time of 1 s. the rc time constant should be approximately 3 s or faster. p hase -l ocked l oop and f requency s ynchroni z ation the ltc3886 has a phase-locked loop ( pll) comprised of an internal voltage-controlled oscillator ( vco) and a phase detector. the pll is locked to the falling edge of the sync pin. the phase relationship between the pwm controller and the falling edge of sync is controlled by the lower 3? bits of the mfr_pwm_config_ lt c 3886 com - mand. for polyphase applications, it is recommended all the phases be spaced evenly. thus for a 2- phase system the signals should be 180 out of phase and a 4-phase system should be spaced 90. the phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators . this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen - tary current sources that charge or discharge the internal filter network. the pll lock range is guaranteed between 100khz and 750 khz. nominal parts will have a range be - yond this; however, operation to a wider frequency range is not guaranteed. the pll has a lock detection circuit. if the pll should lose lock during operation, bit 4 of the status _ mfr _ specific command is asserted and the alert pin is pulled low. the fault can be cleared by writing a 1 to the bit. if the user does not want the alert pin to assert if a pll_fault occurs, the smbalert_mask command can be used to prevent the alert. if there is no external signal applied to the sync pin in the application, the nominal programmed frequency will control the pwm circuitry. if frequency_switch is programmed to external oscillator, and no external sync signal is present, the ltc3886 pwm engine will run at the lowest free running frequency of the pll oscillator. this may result in excess inductor current and undesirable operation. if multiple parts share the sync signal and the external sync signal is not present, the parts will not be synchronized and excess voltage ripple on the output may be present. ltc 3886 3886f 52 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion multiple ltc3886s are required to share one sync signal in polyphase configurations, for other configurations connecting the sync pins to form a single sync signal is optional. if the sync pin is shared between ltc3886s, only one ltc3886 should be programmed with a frequency output. all the other ltc3886s should be programmed to disable their sync output. however their frequency should be programmed to the nominal desired value.if the ltc3886 is programmed with a frequency output, and an external signal is present. bit 10 of mfr_pads_ lt c 3886 will be asserted low if this condition exists. if the pwm signal appears to be running at too high a frequency, monitor the sync pin. extra transitions on the falling edge will result in the pll trying to lock on to noise versus the intended signal. review routing of digital control signals and minimize crosstalk to the sync signal to avoid this problem. m inimum o n -t ime c onsiderations minimum on-time, t on(min) , is the smallest time duration that the ltc3886 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn off the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out v in ? f osc if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc3886 is approximately 90ns. good pcb layout, minimum 30% inductor current ripple and at least 10 mv to 15 mv ripple on the current sense signal are required to avoid increasing the minimum on-time. the minimum on-time can be affected by pcb switching noise in the voltage and current loop. as the peak current sense voltage decreases, the minimum on-time gradually increases to 130 ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. e xternal t emperature s ense the ltc3886 is capable of measuring the temperature of the power stage temperature of each channel. multiple methods using silicon junction remote sensors are supported. the voltage produced by the remote sense circuit is digitized by the internal adc, and the computed temperature value is returned by the paged read_temperature_1 telem- etry command. the most accurate external temperature measurement can be made using a diode-connected pnp transistor such as the mmbt3906 as shown in figure 25. bit 5 of mfr_pwm_mode_ lt c 3886 should be set to 0 (v be method) when using this sensor configuration. the tran- sistor should be placed in contact with or immediately adjacent to the power stage inductor. its emitter should be connected to the tsns n pin while the base and col - lector terminals of the pnp transistor must be connected and returned directly to pin 53 of the ltc3886 using a kelvin connection. for best noise immunity, the connec - tions should be routed differentially and a 10 nf capacitor shou ld be placed in parallel with the diode-connected pnp. parasitic pcb trace inductance between the capacitor and transistor should be minimized. avoid placing pcb vias between the transistor and capacitor. the ltc3886 also supports direct junction voltage measurements when bit 5 of mfr_ pwm_ mode_ lt c 3886 is set to one. the factory defaults support a resistor- trimmed dual diode network as shown in figure 33. this second measurement method is not generally as accurate as the first, but it supports legacy power blocks or may prove necessar y if high noise environments prevent use of the ?v be approach with its lower signal levels. for either method, the slope of the external temperature sensor can be modified with the coefficient stored in mfr_temp_1_gain. with the ?v be approach, typical pnps require temperature slope adjustments slightly ltc 3886 3886f 53 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion less than 1. the mmbt3906 has a recommended value of approximately mfr_temp_1_gain ? = 0.991 based on the ideality factor of 1.01. simply invert the ideality factor to calculate the mfr _ temp_1_gain. different manufacturers and different lots may have different ideality factors. consult with the manufacturer to set this value. characterization over temperature of a prototype or prototypes is recommended before selecting a final mfr_temp_1_gain value when using the direct p-n junction measurement method. the offset of the external temperature sense can be adjusted using mfr_temp_1_offset. if an external temperature sense element is not used, the tsnsn pin must be shorted to gnd. the ut_ fault_ limit must be set to C275c , the ut_ fault_ response must be set to ignore, and the iout_cal_gain_tc to a value of 0. to ensure proper use of these temperature adjustment parameters, refer to the specific formulas given for the two methods in the mfr_pwm_mode_ lt c 3886 com - mand section. derating eeprom retention at temperature eeprom read operations between C40 c and 125 c will not affect data storage. but retention will be degraded if the eeprom is written above 85 c or stored or operated above 125 c. if an occasional fault log is generated above 85c, the slight reduction in data retention in the eeprom fault log area will not affect the use of the function or other eeprom storage. see the operation section for other high temperature eeprom functional details. degradation in data can be approximated by calculating the dimensionless acceleration factor using the following equation. af = e ea k ? ? ? ? ? ? ? 1 t use + 273 C 1 t stress + 273 ? ? ? ? ? ? ? ? ? ? ? ? where: af = acceleration factor ea = activation energy = 1.4ev k = 8.617 ? 10 C5 ev/k t use = is the specified junction temperature t stress = actual junction temperature in c as an example, if the device is stored at 130 c for 10 hours, t stress = 130c, and af = e 1.4 8.617 ? 10 C5 ? ? ? ? ? ? ? 1 398 C 1 403 ? ? ? ? ? ? ? ? ? ? ? ? = 1.66 indicating the effect is the same as operating the device at 125c for 10 ? 1.66 = 16.6 hours, resulting in a retention derating of 6.6 hours. i nput c urrent s ense a mplifier the ltc3886 input current sense amplifier can sense the supply current into the v in pin using an external resistor as well as the power stage current using an external sense resistor. unless care is taken to mitigate the frequency noise caused by the discontinuous input current, significant input current measurement error may occur. the noise will be the greatest in high current applications and at large step- down ratios. careful layout and filtering at the v in pin is recommended to minimize measurement error. the v in pin should be filtered with a resistor and a ceramic capacitor. the filter should be located as close to the v in pin as possible. the supply side of the v in pin filter should be kelvin connected to the supply side of the r iinsns resistor. a 2 resistor should be sufficient for most applications. tsns mmbt3906 ltc3886 10nf gnd gnd 3886 f32 tsns ltc3886 1nf 495a 1.35v at 25c gnd gnd 3886 f33 figure 32. external v be temperature sense figure 33. 2d+r temperature sense ltc 3886 3886f 54 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion the resistor will cause an ir voltage drop from the supply to the v in pin due to the current flowing into the v in pin. to compensate for this voltage drop, the mfr_ rvin command value should be set to the nominal resistor value. the ltc3886 will multiply the mfr_ read_ ichip measurement value by the user defined mfr_ rvin value and add this voltage to the measured voltage at the v in pin. read_ vin = v vin_ pin + (mfr_ read_ ichip ? mfr_ rvin ) therefore, the read_ vin command will return the value of the voltage at the supply side of the v in pin filter. if no v in filter element is used, set mfr_ rvin = 0. the capacitor from the drain of the topside mosfet to ground should be a low esr ceramic capacitor. it should be placed as close as possible to the drain of the topside mosfet to supply high frequency transient input current. this will help prevent noise from the top gate mosfet from feeding into the input current sense amplifier inputs and supply. if the input current sense amplifier is not used, short the v in , i in + and i in C and pins together. e xternal r esistor c onfiguration p ins (rconfig) the ltc3886 is factory programmed to use external resistor configuration. this allows output voltage, pwm frequency, pwm phasing, and the pmbus address to be set by the user without programming the part through the pmbus interface or purchasing custom programmed parts. to use resistor programming, the rconfig pin(s) require a resistor divider between v dd25 and gnd. the rconfig pins are only interrogated at initial power up and during a reset, so modifying their values on the fly while the part is powered will have no effect. rconfig pins on the same ic can be shared with a single resistor divider if they require identical programming. resistors with a tolerance of 1% or better must be used to assure proper operation. in the following tables, r top is connected between v dd25 and the rconfig pin while r bot is connected between the pin and gnd. noisy clock signals should not be routed near these pins. voltage selection when an output voltage is set using the vout_cfg n pins the following parameters are set as a percentage of the output voltage: n vout _ ov _ fa ult _ limit ................................... +10% n vout _ ov _ war n _ limit .................................. +7. 5% n vout _ max ....................................................... +7 . 5% n vout _ margin _ hig h ......................................... +5% n vout _ margin _ low .......................................... C5% n vout _ uv _ war n _ limit ................................. C6 .5% n vout _ uv _ fa ult _ limit ..................................... C7% refer to table 3 to set the output voltage using the vout_cfgn pins. table 3. vout_cfg n r top (k) r bottom (k) v out (v) 0 or open open eeprom 10 23.2 12.0 10 15.8 8.0 16.2 20.5 7.0 16.2 17.4 6.0 20 17.8 5.0 20 15 3.3 20 12.7 2.5 20 11 1.8 24.9 11.3 1.5 24.9 9.09 1.2 24.9 7.32 1.1 24.9 5.76 1.0 24.9 4.32 0.9 30.1 3.57 0.75 30.1 1.96 0.65 open 0 output off* (v out from eeprom) 10f r iinsns m1 m2 10f tg bg sw i in - i in + v in ltc3886 v in 2 3886 f34 figure 34. low noise input current sense circuit ltc 3886 3886f 55 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion frequency selection the pwm switching frequency is set according to table 4. the sync pins must be shared in poly-phase configura - tions where multiple ltc3886s or multiple ltc3886s and ltc3870s are used to produce the output. if the configu- ration is not polyphase the sync pins do not have to be shared. if the sync pins are shared between ltc3886s only one sync pin should be enabled, all other sync pins should be disabled. a pull-up resistor to v dd33 is required on the sync pin. for example in a 4- phase configuration clocked at 250khz, all of the ltc3886s must be set to the desired frequency and phase and one ltc3886 should be set to the desired frequency with the sync pin disabled. all phasing is with respect to the falling edge of sync. for ltc3886 chip 1, set the frequency to 250 khz with 90 and 270 phase shift with the sync pin enabled: frequency: r top = 24.9k and r bot = 11.3k phase: r top = 30.1k and r bot = 1.96k for ltc3886 chip 2, set the frequency to 250 khz with 0 and 180 phase shift and the sync pin disabled: frequency: r top = 24.9k and r bot = 11.3k phase: r top = 24.9k and r bot = 11.3k all configurations in frequency and phase can be achieved using the freq_cfg and phas_cfg pins. in the above application, if the sync pin connection is lost from chip?1, chip 2 will internally detect the frequency as missing and continue switching at 250 khz. however, because the sync pin is disconnected between the chips, the output voltage ripple will likely be higher than desired. bit 10 of mfr_pads will assert low on chip 2 indicating chip 2 is providing its own internal oscillator when it is expecting an external sync input. table 4. freq_cfg resistor programming r top (k) r bot (k) switching frequency (khz) 0 or open open eeprom 10 23.2 eeprom 10 15.8 750 r top (k) r bot (k) switching frequency (khz) 16.2 20.5 650 16.2 17.4 575 20 17.8 500 20 15 425 20 12.7 350 20 11 300 24.9 11.3 250 24.9 9.09 225 24.9 7.32 200 24.9 5.76 175 24.9 4.32 150 30.1 3.57 125 30.1 1.96 100 open 0 external sync only phase selection the phase of the channels with respect to the falling edge of sync is set using the values in table 5. table 5. phas_cfg resistor programming r top (k) r bot (k) sync to 0 sync to 1 sync output 0 or open open eeprom eeprom eeprom 10 23.2 eeprom eeprom eeprom 10 15.8 eeprom eeprom eeprom 16.2 20.5 120 300 disabled 16.2 17.4 60 240 20 12.7 120 240 20 15 0 120 20 12.7 0 240 20 11 90 270 24.9 11.3 0 180 24.9 9.09 120 300 enabled 24.9 7.32 60 240 24.9 5.76 120 240 24.9 4.32 0 120 30.1 3.57 0 240 30.1 1.96 90 270 open 0 0 180 ltc 3886 3886f 56 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion address selection using rconfig the ltc3886 address is selected based on the programming of the two configuration pins asel0 and asel1 according to table 6. asel0 programs the bottom four bits of the device address for the ltc3886, and asel1 programs the three most- significant bits. either portion of the address can also be retrieved from the mfr_address value in eeprom. if both pins are left open, the full 7- bit mfr_address value stored in eeprom is used to determine the device address. the ltc3886 always responds to 7- bit global addresses 0 x5a and 0 x5b. mfr_address should not be set to either of these values because these are global addresses and all parts will respond to them. table 6. asel n resistor programming r top (k) r bot (k) asel1 asel0 ltc3886 device address bits[6:4] ltc3886 device address bits[3:0] binary hex binary hex 0 or open open eeprom eeprom 10 23.2 1 f 10 15.8 10 e 16.2 20.5 101 d 16.2 17.4 100 c 20 17.8 101 b 20 15 1010 a 20 12.7 1001 9 20 11 1000 8 24.9 11.3 111 7 0111 7 24.9 9.09 110 6 0110 6 24.9 7.32 101 5 0101 5 24.9 5.76 100 4 0100 4 24.9 4.32 011 3 0011 3 30.1 3.57 010 2 0010 2 30.1 1.96 001 1 0001 1 open 0 000 0 0000 0 e fficiency c onsiderations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3886 circuits : 1) ic v in current , 2) intv cc regulator current , 3) i 2 r losses , 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. supplying the intv cc current from the extv cc pin with an external supply will reduce the v in current required to a minimum . 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a cur- rent out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. 3. i 2 r losses are predicted from the dc resistances of the fuse ( if used), mosfet, inductor and current sense resistor. in continuous mode, the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds ( on ) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to ob- tain i 2 r losses. for example, if each r ds(on) = 10 m?, r l = 10 m?, r sense = 5 m?, then the total resistance is 25 m?. this results in losses ranging from 2% to 8% as the output current increases from 3 a to 15 a for a 5 v output, or a 3% to 12% loss for a 3.3 v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages ltc 3886 3886f 57 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become significant only when operating at high input voltages (typically 15 v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 i o(max) c rss f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has ad- equate charge storage and very low esr at the switching frequency. a 25 w supply will typically require a minimum of 20 f to 40 f of capacitance having a maximum of 20m ? to 50 m? of esr. the ltc3886 2-phase architecture typically halves this input capacitance requirement over competing solutions. other losses including schottky con - duction losses during dead time and inductor core losses generally account for less than 2% total additional loss. p rogrammable l oop c ompensation the ltc3886 offers programmable loop compensation to optimize the transient response without any hardware change. as shown in figure 35, the error amplifier gain g m varies from 1.0 mmho to 5.73 mmho, and the compen- sation resistor r th varies from 0 k to 62 k inside the controller. tw o compensation capacitors, c th and c thp , are required in the design and the typical ratio between c th and c thp is 10. ? + v ref fb 3886 f52 c thp c th ith r th ith_r g m figure 35. programmable loop compensation by adjusting the g m and r th only, the ltc3886 can provide a flexible type ii compensation network to optimize the loop over a wide range of output capacitors. adjusting the g m will change the gain of the compensation over the whole frequency range without moving the pole and zero location, as shown in figure 36. increase g m frequency 3886 f53 gain type ii compensation figure 36. error amp g m adjust adjusting the r th will change the pole and zero location, as shown in figure 37. it is recommended that the user determines the appropriate value for the g m and r th using the ltpowercadtool. increase r th frequency 3886 f54 gain type ii compensation figure 37. r ith adjust c hecking t ransient r esponse the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load ( esr), where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that ltc 3886 3886f 58 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion forces the regulator to adapt to the current change and return v out to its steady-state value. during this recov- ery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i thr external capacitor shown in the typical application circuit will provide an adequate starting point for most applications. the programmable parameters that affect loop gain are the voltage range, bit[1] of the mfr_pwm_ config_ltc3886 command, the current range, bit 7 of the mfr _ pwm _ mode _ ltc3886 command, the gm of the pwm channel amplifier, bits [7:5] of mfr_pwm_comp, and the internal r ith compensation resistor, bits[4:0] of mfr_pwm_comp. be sure to establish these settings prior to compensation calculation. the i th series internal r ith - external c c filter sets the dominant pole-zero loop compensation. the internal r ith value can be modified (from 0 to 62 k) using bits[4:0] of the mfr_pwm_comp command. adjust the value of r ith to optimize transient response once the final pc layout is done and the particular c c filter capacitor and output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1 s to 10 s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet with a resistor to ground directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a load step. the mosfet + r series will produce output currents approximately equal to v out /r series . r series values from 0.1 to 2 are valid depending on the current limit settings and the programmed output voltage. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r ith and the bandwidth of the loop will be increased by decreasing c c . if r ith is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the gain of the loop will be proportional to the transconductance of the error amplifier which is set using bits[7:5] of the mfr_pwm_comp command. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10 f capacitor would require a 250 s rise time, limiting the charging current to about 200ma. polyphase c onfiguration when configuring a polyphase rail with multiple ltc3886 s, the user must share the sync, ith, share _ clk, faultn , pgoodn and alert pins of both parts. be sure to use pull-up resistors on faultn , pgoodn , sync, share_clk and alert . one of the ltc3886s sync pin must be set to the desired switching frequency, and all other frequency_switch commands must be set to external clock. if an external oscillator is provided, set the frequency_switch command to external clock for all ltc3886s. the relative phasing of all the channels should be spaced equally. the mfr_rail_address of all the devices should be set to the same value. when connecting a polyphase rail with ltc3886s , connect ltc 3886 3886f 59 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion ltc3886 gnd i in ? i sense + i sense ? v in v dd25 v dd33 i th v sense ? v sense + run sync tsns tg sw boost bg intv cc i in + c1 v in r iinsns + q1 l m1 1f ceramic c b 3886 f35 c in + c intvcc m2 d1 c out v out r sense + c vin r vin r l1 d1 l1 sw1 r sense1 v out1 c out1 v in c in r in r l0 d0 bold lines indicate high switching current. keep lines to a minimum length. l0 sw0 3886 f36 r sense0 v out0 c out0 figure 38. recommended printed circuit layout diagram, single phase shown figure 39. branch current waveforms ltc 3886 3886f 60 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion the v in pins of the ltc3886s directly back to the supply voltage through the v in pin filter networks. pc b oard l ayout c hecklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 38. figure 39 illustrates the cur - rent waveforms present in the various branches of the synchronous regulator operating in the continuous mode. check the following in your layout: 1. is the top n-channel mosfet, m1, located within 1 cm of c in ? 2. are signal ground and power ground kept separate? the ground return of c intvcc must return to the combined c out (C) terminals. 3. the i th trace should be as short as possible. 4. the loop formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. 5. the ou tput capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described in item 4. 6. are the i sense + and i sense C leads routed together with minimum pc trace spacing? the filter capacitor between i sense + and i sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 7. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet driver current peaks. an additional 1 f ceramic capacitor placed immediately next to the intv cc and gnd pins can help improve noise performance substantially. 8. keep the switching nodes (swn ), top gate nodes ( tgn ), and boost nodes ( boostn ) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3886 and occupy minimum pc trace area. if dcr sensing is used, place the top resistor (figure 25 a, r1) close to the switching node. 9. use a modified star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc and extv cc decoupling capacitors, the bottom of the voltage feedback resistive divider and the gnd pin of the ic. 10. are the i in + and i in C pins kelvin connected to the r sensein sense resistor? this will prevent the pcb trace resistance from causing errors in the input current measurement. these traces should be as short as possible and routed away from any noisy nodes such as the switching or boost nodes. 11. is the v in filter kelvin connected to the input side of the r sensein resistor? this can help improve the noise performance of the input current sense amplifier by reducing the voltage transients between the amplifier inputs and amplifier supply caused by the discontinuous power stage current. pc b oard l ayout d ebugging it is h elpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (swn pin) to synchronize the oscil - loscope to the in ternal oscillator and probe the actual output voltage as well. check for proper performance over the oper - ating voltage and current range expected in the application . the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold. t he d uty cycle percentage should be maintained from cycle to cycle in a well- designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug - gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. ltc 3886 3886f 61 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion 20k 12.7k 10k 23.2k 10k 23.2k 10k 23.2k 24.9k 11.3k intv cc tg0 tg1 boost0 boost1 sw0 sw1 bg0 sync pgood0 pgood1 sda scl v out0_cfg v dd25 v out1_cfg asel0 asel1 freq_cfg v dd33 alert fault0 fault1 share_clk run0 run1 wp phas_cfg 5k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k v sense0 + v sense0 ? i th0 i thr0 v sense1 extv cc i th1 i thr1 bg1 tsns0 0.22f 6.04k 3.01k 12.1k 6.04k 1f 220pf 10nf 10nf v out1 12v 5a 530f 530f 3886 f37 2200pf v out0 3.3v 10a 2200pf l0: wrth 7443551370 3.7h l1: wrth 74435561100 10h m1, m2: infineon bsc039n06ns m3, m4: infineon bsc014n06ns 0.47f 4.7f tsns1 i sense0 + i sense1 + i sense0 ? i sense1 ? 10f 1f d1 d2 5m 10f 22f 2 v in 18v to 48v 0.1f 0.1f l0 3.7h 3.01k 6.04k 1f m1 m3 m2 m4 1f v in ltc3886 gnd v dd33 v dd25 i in + i in ? l1 10h 1f 220pf + + figure 40. high efficiency dual 250khz 12v/3.3v step-down converter reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un- dervoltage lockout cir cuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out - put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost n , swn, tgn , and possibly bgn connections and the sensitive volt - age and current pins. the capacitor placed across the cur- rent sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the gnd pin of the ic. ltc 3886 3886f 62 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion d esign e xample as a design example for a medium current regulator, assume v in = 48 v nominal, v in = 55 v maximum, v out0 = 3.3 v, v out1 = 12 v, i max0,1 = 10 a and f = 250khz (see figure 40). the regulated outputs are established by the vout_ command stored in eeprom or placing the following resistor divider between v dd25 the v outn _ cfg pin and gnd: 1. v out0_cfg , r top = 20k, r bottom = 12.7k 2. v out1_cfg , r top = 10k, r bottom = 23.2k the frequency and phase are set by eeprom or by setting the resistor dividers between v dd25 and gnd. 1. freq_cfg, r top = 24.9k, r bottom = 11.3k 2. phas_cfg, r top = open, r bottom = 0 the address is set to xf where x is the msb stored in eeprom. the following parameters are set as a percentage of the output voltage if the resistor configuration pins are used to determined output voltage: n vout _ ov _ fa ult _ limit .................................... +10% n vout _ ov _ war n _ limit .................................. +7. 5% n vout _ max ....................................................... +7 . 5% n vout _ margin _ hig h ......................................... +5% n vout _ margin _ low .......................................... C5% n vout _ uv _ war n _ limit .................................. C6 .5% n vout _ uv _ fa ult _ limit ...................................... C7% all other user defined parameters must be programmed into the eeprom. the gui can be utilized to quickly set up the part with the desired operating parameters. the inductance values are based on a 35% maximum ripple current assumption (3.5 a). the highest value of ripple current occurs at the maximum input voltage: l = v out f ? ? i l(max) 1C v out v in(max) ? ? ? ? ? ? ? ? channel 0 will require 3.5 h and channel 1 will require 10.7h. the nearest standard values are 3.7 h and10h respectively. at the nominal input the ripple will be: ? i l(nom) = v out f ? l 1C v out v in(nom) ? ? ? ? ? ? ? ? channel 0 will have 3.32a (33%) ripple, and channel 1 will have 3.6a (36%) ripple. the peak inductor current will be the maximum dc value plus one-half the ripple current or 11.6a for channel 0 and 11.8 a for channel 1. the minimum on time occurs on channel 0 at the maximum v in , and should not be less than 90ns: t on(min) = v out v in(max) ? f = 3.3v 55v 250khz ( ) = 240ns the w rth 7443551370 3.7 h (7 m dcr typ at 25 c) channel 0 and the wurth 744355611000 10 h (7 m dcr typ at 25 c) channel 1 are the chosen inductors . r1 + r3 ( ) ||r2 = 2 ? l dcr at 25 c ( ) ? c1 = 2 ? 3.7h 4.9m ? ? 0.22f = 6.86k set r1 = r3 = 3.48, r2 = 6.81k. iout _cal _gain = dcr ? r2 r1 + r2 + r3 = 2.45m ? the maximum power loss in r1 is related to the duty cycle, and will occur in continuous mode at the maximum input voltage: p loss ? r1 = v in(max) C v out ( ) ? v out r1 = 55 C 3.3 ( ) ? 3.3 3.05k = 55.9mw the respective values for channel 1 are c1 = 0.47 f, r1 = r3 = 6.08 k, r3 = 12.16k, iout_cal_gain = 3.5m and p loss r1 = 84.9mw. ltc 3886 3886f 63 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion the current limit will be set 20% higher than the peak value to assure variation in components and noise in the system do not limit the average current. v ilimit = i peak ? r dcr( max) = 1.2 ?11.3 a ?3.5 m = 47.46mv the closest v ilimit setting is 42.9mv or 48.2 mv. the values are entered with the iout_oc_fault_limit command. based on expected variation and measurement in the lab across the sense capacitor the user can determine the optimal setting. for channel 1 the v ilimit value is 49.56mv. the closest value is 53.6mv. the power dissipation on the topside mosfet can be easily estimated. choose an infineon bsc039n 06ns topside mosfet. r ds( on) = 3.9m , c miller = 75pf. at maximum input voltage with t estimated = 50c and a bottom side infineon bsc014n 06ns mosfet, r ds( on) = 1.45m : p main = 3.3v 55v ? 11.6 ( ) 2 ? 1 + 0.005 ( ) 50 c C 25 c ( ) ? ? ? ? ? 0.0039 ? + 55v ( ) 2 5.8a ( ) ? 1 5 C 2.8 + 1 2.8 ? ? ? ? ? ? 59pf ( ) 250khz ( ) = 0.245w the loss in the bottom side mosfet is: p sync = 55v C 3.3v ( ) 55v ? 11.6a ( ) 2 ? 1 + 0.005 ( ) 50 c C 25 c ( ) ? ? ? ? ? 0.00145 ? = 0.206w both mosfets have i 2 r losses while the p main equation includes an additional term for transition losses, which are highest at high input voltages. the minimum required c in rms current rating is: i rms = 11.8 55 3.3 ( ) ? 55 C 3.3 ( ) ? ? ? ? 1/2 = 2.8a at temperature. c out is chosen with an esr of 0.01 for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is v oripple = r(?i l ) = 0.01 ? 3.6a = 36mv. a dditional d esign c hecks tie fau lt0 and fa u lt1 together and pull up to v dd33 with a 10k resistor. tie run0 and run1 together and pull up to v dd33 with a 10k resistor. if there are other lt c psm parts, connect the run pins between chips and connect the fault pins between chips. be sure all pmbus pins have resistor pull-up to v dd33 and connect these inputs across all lt c psm parts in the application. tie share_clk high with a 10 k resistor to v dd33 and share between all lt c psm parts in the application. be sure a unique address for each chip can be decoded with the asel0 and asel1 pins. refer to table 6. for maximum flexibility, allow board space for r top and r bottom for any parameter that is set with resistors such as asel0 and asel1. c onnecting the usb to i 2 c/smbus/pmbus a dapter to the ltc3886 i n s ystem the lt c usb to i 2 c/smbus/pmbus adapter ( dc1613a or equivalent) can be interfaced to the ltc3886 on the users board for programming, telemetry and system debug. the adapter, when used in conjunction with ltpowerplay, provides a powerful way to debug an entire power system. faults are quickly diagnosed using telemetry, fault status commands and the fault log. the final configuration can be quickly developed and stored to the ltc3886 eeprom. figure 41 illustrates the application schematic for powering, programming and communication with one or more ltc3886s via the ltc i 2 c/smbus/pmbus adapter regardless of whether or not system power is present. if system power is not present, the adapter will power the ltc3886 through the v dd33 supply pin. to initialize the part when v in is not applied and the v dd33 pin is powered use global address 0 x5b command 0 xbd data 0x2b followed by address 0 x5b command 0 xbd data 0xc4. the ltc3886 will now communicate normally, and the project file can be updated. to write the updated project file to the eeprom issue a store_user_all command. ltc 3886 3886f 64 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion v in v in v dd33 v dd25 sda 1f 1f vgs max on the tp0101k is 8v if v in > 16v change the resistor divider on the pfet gate 1f 1f 3886 f38 10k 100k tp0101k isolated 3.3v sda scl tp0101k 100k lt c controller header to ltc dc1613 usb to i 2 c/smbus/pmbus controller scl wp gnd ltc3886 v in v dd33 sda scl wp gnd ltc3886 10k v dd25 figure 41. lt c controller connection when vin is applied, a mfr_reset must be issued to allow the pwm to be enabled and valid adcs to be read. because of the adapter s limited current sourcing capabil - ity, only the ltc3886s, their associated pull-up resistors and the i 2 c pull-up resistors should be powered from the ored 3.3 v supply. in addition any device sharing the i 2 c bus connections with the ltc3886 should not have body diodes between the sda/scl pins and their respective v dd node because this will interfere with bus communication in the absence of system power. if v in is applied the dc1613a will not supply power to the ltc3886s on the board. it is recommended the run n pins be held low or no voltage configuration resistors inserted to avoid providing power to the load until the part is fully configured. the ltc3886 is fully isolated from the host pcs ground by the dc1613a. the 3.3 v from the adapter and the ltc3886 v dd33 pin must be driven to each ltc3886 with a sepa- rate pfet. if v in is not applied, the v dd33 pins can be in parallel because the on-chip ldo is off. the dc1613as 3.3v current limit is 100 ma but typical v dd33 currents are under 15 ma. the v dd33 does back drive the intv cc / extv cc pins. normally this is not an issue if v in is open. ltpowerplay: a n i nteractive gui for d igital p ower ltpowerplay is a powerful windows-based development environment that supports linear technology digital power ics including the ltc3886. the software sup - ports a variety of different tasks. ltpowerplay can be used to evaluate linear technology ics by connecting to a demo board or the user application. ltpowerplay can also be used in an offline mode ( with no hardware pres - ent) in order to build multiple ic configuration files that can be saved and re-loaded at a later time. ltpowerplay provides unprecedented diagnostic and debug features. it becomes a valuable diagnostic tool during board bring- up to program or tweak the power system or to diagnose power issues when bringing up rails. ltpowerplay utilizes linear technologys usb-to-i 2 c/smbus/pmbus adapter to communication with one of the many potential targets including the dc2155a demo board, or a customer target system. the software also provides an automatic update feature to keep the revision current with the latest set of device drivers and documentation. a great deal of context sensitive help is available with ltpowerplay along with several tutorial demos. complete information is available at: http://www.linear.com/ltpowerplay ltc 3886 3886f 65 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion pmbus c ommunication and c ommand p rocessing the ltc3886 has a one deep buffer to hold the last data written for each supported command prior to processing as shown in figure 43; write command data processing. when the part receives a new command from the bus, decoder cmd internal processor write command data buffer page cmds 0x00 0x21 0xfd 3886 f40 x1 ? ? ? ? ? ? mfr_reset vout_command s calculations pending pmbus write r fetch, convert data and execute data mux figure 43. write command data processing figure 42. ltpowerplay screen shot it copies the data into the write command data buffer, indicates to the internal processor that this command data needs to be fetched, and converts the command to its internal format so that it can be executed. tw o distinct parallel blocks manage command buffering and command processing ( fetch, convert, and execute) to ensure the last data written to any command is never lost. command data buffering handles incoming pmbus writes by storing the command data to the write command data buffer and marking these commands for future process - ing. the internal processor runs in parallel and handles the sometimes slower task of fetching, converting and executing commands marked for processing. some computationally intensive commands ( e.g., timing parameters, temperatures, voltages and currents) have internal processor execution times that may be long relative ltc 3886 3886f 66 for more information www.linear.com/ltc3886 a pplica t ions i n f or m a t ion // wait until chip is not busy do { mfrcommonvalue = pmbus_read_byte(0xef); partready = (mfrcommonvalue & 0x68) == 0x68; }while(!partready) // now the part is ready to receive the next command pmbus_write_word(0x21, 0x2000); //write vout_command to 2v figure 44. example of a command write of vout_command because it is in a transitional vout state ( margining hi/lo, power off/on, moving to a new output voltage set point, etc.) it will clear bit 4 of mfr_common ( output not in transition). when internal calculations are in process, the part will clear bit?5 of mfr_common ( calculations not pending). these three status bits can be polled with a pmbus read byte of the mfr_common register until all three bits are set. a command immediately following the status bits being set will be accepted without nacking or generating a busy fault/ alert notification. the part can nack commands for other reasons, however, as required by the pmbus spec ( for instance, an invalid command or data). an example of a robust command write algorithm for the vout_command register is provided in figure 44. it is recommended that all command writes ( write byte, write word, etc . ) be preceded with a polling loop to avoid the extra complexity of dealing with busy behavior and unwanted alert notification. a simple way to achieve this is to create a safe_write_byte() and safe_write_ word() subroutine. the above polling mechanism allows your software to remain clean and simple while robustly communicating with the part. for a detailed discussion of these topics and other special cases please refer to the application note section located at: www.linear.com/designtools/app_notes when communicating using bus speeds at or below 100khz, the polling mechanism shown here provides a simple solution that ensures robust communication without clock stretching. at bus speeds in excess of 100 khz, it is strongly recommended that the part be configured to en - able clock stretching. this requires a pmbus master that supports clock stretching. system software that detects and properly recovers from the standard pmbus nack/ busy faults as described in the pmbus specification v1.1, part ii, section 10.8.7 is required to communicate the ltc3886 is not recommended in applications with bus speeds in excess of 400khz to pmbus timing. if the part is busy processing a command, and new command(s) arrive, execution may be delayed or processed in a different order than received. the part indicates when internal calculations are in process via bit ?5 of mfr_common ( calculations not pending). when the part is busy calculating, bit 5 is cleared. when this bit is set, the part is ready for another command. an example polling loop is provided in figure 44 which ensures that commands are processed in order while simplifying error handling routines. when the part receives a new command while it is busy, it will communicate this condition using standard pmbus protocol. depending on part configuration it may either nack the command or return all ones (0 xff) for reads. it may also generate a busy fault and alert notification, or stretch the scl clock low. for more information refer to pmbus specification v1.1, part ii, section 10.8.7 and smbus v2.0 section 4.3.3. clock stretching can be enabled by asserting bit 1 of mfr_config_all_ lt c 3886. clock stretching will only occur if enabled and the bus com - munication speed exceeds 100khz. pmbus busy protocols are well accepted standards, but can make writing system level software somewhat com - plex. the part provides three hand shaking status bits which reduce complexity while enabling robust system level communication. the three hand shaking status bits are in the mfr_ common register. when the part is busy executing an internal operation, it will clear bit 6 of mfr_common (chip not busy). when the part is busy specifically ltc 3886 3886f 67 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails a ddressing and w rite p rotect command name cmd code description type paged d ata format units eeprom default value page 0x00 provides integration with multi-page pmbus devices. r/w byte n reg 0x00 page_plus_write 0x05 write a supported command directly to a pwm channel. w block n page_plus_read 0x06 read a supported command directly from a pwm channel. block r/w n write_protect 0x10 level of protection provided by the device against accidental changes. r/w byte n reg y 0x00 mfr_address 0xe6 sets the 7-bit i 2 c address byte. r/w byte n reg y 0x4f mfr_rail_address 0 xfa common address for polyphase outputs to adjust common parameters. r/w byte y reg y 0x80 page the page command provides the ability to configure, control and monitor both pwm channels through only one physical address, either the mfr_address or global device address. each page contains the operating commands for one pwm channel. pages 0x00 and 0x01 correspond to channel 0 and channel 1, respectively, in this device. setting page to 0 xff applies any following paged commands to both outputs. reading from the device with page set to 0xff is not recommended. this command has one data byte. page_plus_write the page_plus_write command provides a way to set the page within a device, send a command, and then send the data for the command, all in one communication packet. commands allowed by the present write protection level may be sent with page_plus_write. the value stored in the page command is not affected by page_plus_write. if page_plus_write is used to send a non-paged command, the page number byte is ignored. this command uses write block protocol. an example of the page_plus_write command with pec sending a com - mand that has two data bytes is shown in figure 45. slave address page_plus command code block count (= 4) w a a s 7 8 8 1 page number 8 1 1 1 1 1 a a ? command code 8 1 a upper data byte a a p 3886 f42 a 8 8 1 1 1 1 pec byte lower data byte 8 figure 45. example of page_plus_write ltc 3886 3886f 68 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails page_plus_read the page_plus_read command provides the ability to set the page within a device, send a command, and then read the data returned by the command, all in one communication packet . the value stored in the page command is not affected by page_plus_read. if page_plus_read is used to access data from a non-paged command, the page number byte is ignored. this command uses block write-block read process call protocol. an example of the page_plus_read command with pec is shown in figure 46. p 1 slave address page_plus command code block count (= 2) w a a s 7 8 8 1 page number 8 1 1 1 1 1 a a ? command code 8 1 a slave address block count (= 2) lower data byte r a a sr 7 8 8 1 upper data byte 8 1 1 1 1 1 a a pec byte 8 1 na 3886 f43 figure 46. example of page_plus_read note: page_plus commands cannot be nested. a page_plus command cannot be used to read or write another page_plus command. if this is attempted, the ltc3886 will nack the entire page_plus packet and issue a cml fault for invalid/unsupported data. write_protect the write_protect command is used to control writing to the ltc3886 device. this command does not indicate the status of the wp pin which is defined in the mfr_common command. the wp pin takes precedence over the value of this command. byte meaning 0x80 disable all writes except to the write_protect, page, mfr_ ee_unlock, and store_user_all command. 0x40 disable all writes except to the write_protect, page, mfr_ee_unlock, mfr_clear_peaks, store_user_all, operation and clear_faults command. individual fault bits can be cleared by writing a 1 to the respective bits in the status commands. 0x20 disable all writes except to the write_protect, operation, mfr_ee_unlock, mfr_clear_peaks, clear_faults, page, on_off_config, vout_command and store_user_ all. individual fault bits can be cleared by writing a 1 to the respective bits in the status commands. 0x10 reserved, must be 0 0x08 reserved, must be 0 0x04 reserved, must be 0 0x02 reserved, must be 0 0x01 reserved, must be 0 ltc 3886 3886f 69 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails when write_protect is set to 0x00, writes to all commands are enabled. if wp pin is high, page, operation, mfr _ clear_ peaks, mfr _ ee_ unlock, write _ protect and clear_ faults commands are supported. individual fault bits can be cleared by writing a 1 to the respective bits in the status commands. mfr_address the mfr_address command byte sets the 7 bits of the pmbus slave address for this device. setting this command to a value of 0 x80 disables device addressing. the global device address, 0 x5a and 0x5b, cannot be deactivated. if rconfig is set to ignore, the asel0 and asel1 pins are still used to determine the lsb and msb, respectively, of the channel address. if the asel0 and asel1 pins are both open, the ltc3886 will use the address value stored in eeprom. if the asel0 pin is open, the ltc3886 will use the lower 4 bits of the mfr_address value stored in eeprom to construct the effective address of the part. if the asel1 pin is open, the ltc3886 will use the upper 3 bits of the mfr_address value stored in eeprom to construct the effective address of the part. this command has one data byte. mfr_rail_address the mfr_rail_address command enables direct device address access to the page activated channel. the value of this command should be common to all devices attached to a single power supply rail. the user should only perform command writes to this address. if a read is performed from this address and the rail devices do not respond with exactly the same value, the ltc3886 will detect bus contention and may set a cml communications fault. setting this command to a value of 0x80 disables rail device addressing for the channel. this command has one data byte. g eneral c onfiguration commands command name cmd code description type paged d ata format units eeprom default value mfr_chan_config_ lt c 3886 0xd0 configuration bits that are channel specific. r/w byte y reg y 0x1d mfr_config_all_ lt c 3886 0xd1 general configuration bits. r/w byte n reg y 0x21 ltc 3886 3886f 70 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails mfr_chan_config_ ltc 3886 general purpose configuration command common to multiple lt c products. bit meaning 7 reserved 6 reserved 5 reserved 4 disable run low. when asserted the run pin is not pulsed low if commanded off. 3 short cycle. when asserted the output will immediate off if commanded on while waiting for toff_delay or toff_fall. toff_min of 120ms is honored then the part will command on. 2 share_clock control. if share_clock is held low, the output is disabled. 1 alert is not pulled low if fault is pulled low externally. 0 disables the v out decay value requirement for mfr_retry_time processing. when this bit is set to a 0, the output must decay to less than 12.5% of the programmed value for any action that turns off the rail including a fault, an off/on command, or a toggle of run from high to low to high. this command has one data byte. mfr_config_all_ ltc 3886 general purpose configuration command common to multiple lt c products. bit meaning 7 enable fault logging 6 ignore resistor configuration pins 5 disable cml fault for quick command message. 4 disable sync output 3 enable 255ms pmbus timeout 2 a valid pec required for pmbus writes to be accepted. if this bit is not set, the part will accept commands with invalid pec. 1 enable the use of pmbus clock stretching 0 execute clear_faults on rising edge of either run pin. this command has one data byte. o n /o ff /m argin command name cmd code description type paged d ata format units eeprom default value on_off_config 0x02 run pin and pmbus bus on/off command configuration. r/w byte y reg y 0x1e operation 0x01 operating mode control. on/off, margin high and margin low. r/w byte y reg y 0x40 mfr_reset 0xfd commanded reset without requiring a power-down. send byte n na ltc 3886 3886f 71 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails on_off_config the on_off_config command specifies the combination of run n pin input state and pmbus commands needed to turn the pwm channel on and off. supported values: value meaning 0x1f operation value and run n pin must both command the device to start/run. device executes immediate off when commanded off. 0x1e operation value and run n pin must both command the device to start/run. device uses toff_ command values when commanded off. 0x17 run n pin control with immediate off when commanded off. operation on/off control ignored. 0x16 run n pin control using toff_ command values when commanded off. operation on/off control ignored. programming an unsupported on_off_config value will generate a cml fault and the command will be ignored. this command has one data byte. operation the operation command is used to turn the unit on and off in conjunction with the input from the run n pins. it is also used to cause the unit to set the output voltage to the upper or lower margin voltages. the unit stays in the commanded operating mode until a subsequent operation command or change in the state of the run n pin instructs the device to change to another mode. if the part is stored in the margin_low/high state, the next reset or power_on cycle will ramp to that state. if the operation command is modified, for example on is changed to margin_low, the output will move at a fixed slope set by the vout_transition_rate. the default operation command is sequence off. if v in is applied to a part with factory default programming and the vout_config resistor configuration pins are not installed, the outputs will be commanded off. the part defaults to the sequence off state. this command has one data byte. supported values: value meaning 0xa8 margin high. 0x98 margin low. 0x80 on (v out back to nominal even if bit 3 of on_off_config is not set). 0x40* soft off (with sequencing). 0x00* immediate off (no sequencing). *device does not respond to these commands if bit 3 of on_off_config is not set. programming an unsupported operation value will generate a cml fault and the command will be ignored. this command has one data byte. ltc 3886 3886f 72 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails mfr_reset this command provides a means to reset the ltc3886 from the serial bus. this forces the ltc3886 to turn off both pwm channels, load the operating memory from internal eeprom, clear all faults and then perform a soft-start of both pwm channels, if enabled. this write-only command has no data bytes. pwm c onfiguration command name cmd code description type paged d ata format units eeprom default value mfr_pwm_comp 0xd3 pwm loop compensation configuration r/w byte y reg y 0x70 mfr_pwm_mode_ lt c 3886 0xd4 configuration for the pwm engine. r/w byte y reg y 0xc1 mfr_pwm_config_ lt c 3886 0xf5 set numerous parameters for the dc/dc controller including phasing. r/w byte n reg y 0x10 frequency_switch 0x33 switching frequency of the controller. r/w word n l11 khz y 350 0xfabc mfr_pwm_mode_ ltc 3886 the mfr_pwm_mode_ lt c 3886 command sets important pwm controls for each channel. bits [0] and [6] may be changed when the addressed channel(s) is on,however the channel(s) must be turned off if any other bits are changed when the command is issued. the ltc3886 will issue a cml fault and ignore the command and its data if the channel is on and any bits other than [0] and [6] are changed. the mfr_pwm_mode_ lt c 3886 command allows the user to program the pwm controller to use discontinuous (pulse-skipping mode), or forced continuous conduction mode. bit meaning 7 0b 1b use high range of i limit low current range high current range 6 enable servo mode 5 external temperature sense: 0: v be measurement. 1: direct voltage measurement. [4:2] reserved 1 0b 1b v out range the maximum output voltage is 13.2v the maximum output voltage is 7v bit[0] 0b 1b mode discontinuous forced continuous bit [7] of this command determines if the part is in high range or low range of the iout_oc_fault_limit command. changing this bit value changes the pwm loop gain and compensation. this bit value cannot be changed when the ltc 3886 3886f 73 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails channel output is active. writing this bit when the channel is active will generate a cml fault. bit [6] the ltc3886 will not servo while the part is off, ramping on or ramping off. when set to a one, the output servo is enabled. the output set point dac will be slowly adjusted to minimize the difference between the read_vout_adc and the vout_command (or the appropriate margined value). when bit[5] is cleared, the ltc3886 computes temperature in c from ?v be measured by the adc at the tsns n pin as t = (g ? v be ? q/(k ? ln(16))) C 273.15 + o when bit[5] is set, the ltc3886 computes temperature in c from tsnsn voltage measured by the adc as t = (g ? (1.35 C v tsnsn + o)/4.3e-3) + 25 for both equations, g = mfr_temp_1_gain ? 2 C14 , and o = mfr_temp_1_offset bit[1] of this command determines if the part is in high range or low voltage range. changing this bit value changes the pwm loop gain and compensation. this bit value cannot be changed when the channel output is active. writing this bit when the channel is active will generate a cml fault. b it[0] determines if the pwm mode of operation is discontinuous ( pulse- skipping mode), or forced continuous conduction mode. this command has one data byte.whenever the channel is ramping on, the pwm mode will be discontinuous, regardless of the value of this command. mfr_pwm_comp the mfr_pwm_comp command sets the gm of the pwm channel error amplifiers and the value of the internal r ithn compensation resistors. this command affects the loop gain of the pwm output which may require modifications to the external compensation network. bit meaning bit [7:5] ea gm (ms) 000b 1.00 001b 1.68 010b 2.35 011b 3.02 100b 3.69 101b 4.36 110b 5.04 111b 5.73 bit [4:0] r ith (k) 00000b 0 00001b 0.25 00010b 0.5 00011b 0.75 00100b 1 00101b 1.25 ltc 3886 3886f 74 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails bit meaning 00110b 1.5 00111b 1.75 01000b 2 01001b 2.5 01010b 3 01011b 3.5 01100b 4 01101b 4.5 01110b 5 01111b 5.5 10000b 6 10001b 7 10010b 8 10011b 9 10100b 11 10101b 13 10110b 15 10111b 17 11000b 20 11001b 24 11010b 28 11011b 32 11100b 38 11101b 46 11110b 54 11111b 62 this command has one data byte. mfr_pwm_config_ ltc 3886 the mfr_pwm_config_ lt c 3886 command sets the switching frequency phase offset with respect to the falling edge of the sync signal. the part must be in the off state to process this command. either the run pins must be low or the part must be commanded off. if either channel is in the run state and this command is written, the command will be nackd and a busy fault will be asserted. bit meaning 7 0b 1b use vfbo feedback nodes of both channels are independent. channel 1 uses the channel 0 feedback node. [6:5] 00b 01b 10b 11b input current sense gain. 2x gain. 0mv to 50mv range. 4x gain. 0mv to 25mv range. 8x gain. 0mv to 5mv range. ltc 3886 3886f 75 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails bit meaning 4 share clock enable : if this bit is 1, the share_clk pin will not be released until v in > vin_on. the share_clk pin will be pulled low when v in < vin_off. if this bit is 0, the share_clk pin will not be pulled low when vin < vin_off except for the initial application of vin. bit [2:0] channel 0 (degrees) channel 1 (degrees) 000b 0 180 001b 90 270 010b 0 240 011b 0 120 100b 120 240 101b 60 240 110b 120 300 do not assert bit[7] except for use in a polyphase configuration. the v sensen + n , i th n , pgoodn and runn must be shared between channels when this bit is asserted. frequency_switch the frequency_switch command sets the switching frequency, in khz, of a pmbus device. supported frequencies: value [15:0] resulting frequency ( typ ) 0x0000 external oscillator 0xeb20 100khz 0xfbe8 125khz 0xf258 150khz 0xf2bc 175khz 0xf320 200khz 0xf384 225khz 0xf3e8 250khz 0 xfa 58 300khz 0xfabc 350khz 0xfb52 425khz 0xfbe8 500khz 0x023f 575khz 0x028a 650khz 0x02ee 750khz the part must be in the off state to process this command. the run pin must be low or both channels must be commanded off. if the part is in the run state and this command is written, the command will be nack'd and a busy fault will be asserted. when the part is commanded off and the frequency is changed, a pll_unlock status may be detected as the pll locks onto the new frequency. this command has two data bytes and is formatted in linear_5s_11s format. ltc 3886 3886f 76 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails v oltage input voltage and limits command name cmd code description type paged d ata format units eeprom default value vin_ov_fault_limit 0x55 input supply overvoltage fault limit. r/w word n l11 v y 48.0 0xe300 vin_uv_warn_limit 0x58 input supply undervoltage warning limit. r/w word n l11 v y 6.3 0xcb26 vin_on 0x35 input voltage at which the unit should start power conversion. r/w word n l11 v y 6.5 0xcb40 vin_off 0x36 input voltage at which the unit should stop power conversion. r/w word n l11 v y 6.0 0xcb00 mfr_rvin 0xf7 the resistance value of the v in pin filter element in milliohms r/w word n l11 m y 3000 0x12ee vin_ov_fault_limit the vin_ov_fault_limit command sets the value of the input voltage measured by the adc, in volts, that causes an input overvoltage fault. this command has two data bytes in linear_5s_11s format. vin_uv_warn_limit the vin_uv_warn_limit command sets the value of input voltage measured by the adc that causes an input undervoltage warning. this warning is disabled until the input exceeds the input startup threshold value set by the vin_on command and the unit has been enabled. if the vin_uv_warn _limit is then exceeded, the device: ? sets the input bit is the status_word ? sets the v in undervoltage warning bit in the status_input command ? notifies the host by asserting alert , unless masked vin_on the vin_on command sets the input voltage, in volts, at which the unit should start power conversion. this command has two data bytes and is formatted in linear_5s_11s format. vin_off the vin_off command sets the input voltage, in volts, at which the unit should stop power conversion. this command has two data bytes and is formatted in linear_5s_11s format. ltc 3886 3886f 77 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails mfr_rvin the mfr_rvin command is used to set the resistance value of the v in pin filter element in milliohms . ( see also read_vin). set mfr_rvin equal to 0 if no filter element is used. this command has two data bytes and is formatted in linear_5s_11s format. output voltage and limits command name cmd code description type paged d ata format units eeprom default value vout_mode 0x20 output voltage format and exponent (2 C12 ). r byte y reg 2 C12 0x14 vout_max 0x24 upper limit on the output voltage the unit can command regardless of any other commands. r/w w ord y l16 v y 14.0 0xe000 vout_ov_fault_ limit 0x40 output over voltage fault limit. r/w word y l16 v y 1.1 0x119a vout_ov_warn_ limit 0x42 output overvoltage warning limit. r/w word y l16 v y 1.075 0x1133 vout_margin_high 0x25 margin high output voltage set point. must be greater than vout_ command. r/w word y l16 v y 1.05 0x10cd vout_command 0x21 nominal output voltage set point. r/w word y l16 v y 1.0 0x1000 vout_margin_low 0x26 margin low output voltage set point. must be less than vout_ command. r/w word y l16 v y 0.95 0x0f33 vout_uv_warn_ limit 0x43 output undervoltage warning limit. r/w word y l16 v y 0.925 0x0ecd vout_uv_fault_ limit 0x44 output undervoltage fault limit. r/w word y l16 v y 0.9 0x0e66 mfr_vout_max 0xa5 maximum allowed output voltage. r word y l16 v 14.0 0xe000 vout_mode the data byte for vout_mode command, used for commanding and reading output voltage, consists of a 3- bit mode (only linear format is supported) and a 5- bit parameter representing the exponent used in output voltage read/write commands. this read-only command has one data byte. vout_max the vout_max command sets an upper limit on any voltage, including vout_margin_high, the unit can command regardless of any other commands or combinations. the maximum allowed value of this command is 14 volts. the maximum output voltage the ltc3886 can produce is 14 volts including vout_margin_high. however, the vout_ov_fault_limit can only be commanded as high as 14 volts. this command has two data bytes and is formatted in linear_16u format. ltc 3886 3886f 78 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails vout_ov_fault_limit the vout_ov_fault_limit command sets the value of the output voltage measured by the ov supervisor compara- tor at the sense pins, in volts, which causes an output overvoltage fault. if the vout_ov_fault_limit is modified and the part is in the run state, allow 10 ms after the command is modified to assure the new value is being honored. the part indicates if it is busy making a calculation. monitor bits 5 and 6 of mfr_common. either bit is low if the part is busy. if this wait time is not met, and the vout_command is modified above the old overvoltage limit, an ov condition might temporarily be detected resulting in undesirable behavior and possible damage to the switcher. if vout_ov_fault_response is set to ov_pulldown or 0 x00, the fault pin will not assert if vout_ov_fault is propagated. the ltc3886 will pull the tg low and assert the bg bit as soon as the overvoltage condition is detected. this command has two data bytes and is formatted in linear_16u format. vout_ov_warn_limit the vout_ov_warn_limit command sets the value of the output voltage measured by the adc at the sense pins, in volts, which causes an output voltage high warning. the mfr_vout_peak value will be used to determine if this limit has been exceeded. in response to the vout_ov_warn_limit being exceeded, the device: ? sets the none_of_the_above bit in the status_byte ? sets the vout bit in the status_word ? sets the vout overvoltage warning bit in the status_vout command ? notifies the host by asserting alert pin, unless masked this condition is detected by the adc so the response time may be up to 120ms. this command has two data bytes and is formatted in linear_16u format. vout_margin_high the vout_margin_high command loads the unit with the voltage to which the output is to be changed, in volts, when the operation command is set to margin high. the value must be greater than vout_command. the maximum guranteed value on vout_margin_high is 13.8 volts. this command will not be acted on during ton_ rise and toff _ fall output sequencing. the vout _ transition _ rate will be used if this command is modified while the output is active and in a steady-state condition. this command has two data bytes and is formatted in linear_16u format. ltc 3886 3886f 79 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails vout_command the vout_command consists of two bytes and is used to set the output voltage, in volts. the maximum guaranteed value on vout is 13.2 volts. this command will not be acted on during ton_ rise and toff _ fall output sequencing. the vout _ transition _ rate will be used if this command is modified while the output is active and in a steady-state condition. this command has two data bytes and is formatted in linear_16u format. vout_margin_low the vout_margin_low command loads the unit with the voltage to which the output is to be changed, in volts, when the operation command is set to margin low. the value must be less than vout_command. this command will not be acted on during ton_ rise and toff _ fall output sequencing. the vout _ transition _ rate will be used if this command is modified while the output is active and in a steady-state condition. this command has two data bytes and is formatted in linear_16u format. vout_uv_warn_limit the vout_uv_ warn_limit command reads the value of the output voltage measured by the adc at the sense pins, in volts , which causes an output voltage low warning. in response to the vout_uv_warn_limit being exceeded, the device: ? sets the none_of_the_above bit in the status_by te ? sets the vout bit in the status_word ? sets the vout undervoltage warning bit in the status_vout command ? notifies the host by asserting alert pin, unless masked this command has two data bytes and is formatted in linear_16u format. vout_uv_fault_limit the vout_uv_fault_limit command reads the value of the output voltage measured by the uv supervisor com - parator at the sense pins, in volts, which causes an output undervoltage fault. this command has two data bytes and is formatted in linear_16u format. mfr_vout_max the mfr_vout_max command is the maximum output voltage in volts for each channel, including vout_ov_fault_ limit. if the output voltages are set to high range ( bit 6 of mfr_pwm_config_ltc3886 set to a 0) mfr_vout_max is 14.0v. if the output voltage is set to low range (bit 6 of mfr_pwm_config_ltc3886 set to a 1) the mfr_vout_max is 7.0 v. entering a vout_command value greater than this will result in a cml fault and the output voltage setting will be clamped to the maximum level. this will also result in bit 3 vout_max_warning in the status_vout com- mand being set. this read only command has 2 data bytes and is formatted in linear_16u format. ltc 3886 3886f 80 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails o utput c urrent and l imits command name cmd code description type paged d ata format units eeprom default value iout_cal_gain 0x38 the ratio of the voltage at the current sense pins to the sensed current. for devices using a fixed current sense resistor, it is the resistance value in m. r/w word y l11 m y 1.8 0xbb9a mfr_iout_cal_gain_tc 0xf6 temperature coefficient of the current sensing element. r/w word y cf y 3900 0x0f3c iout_oc_fault_limit 0x46 output over current fault limit. r/w word y l11 a y 29.75 0xdbb8 iout_oc_warn_limit 0x4a output overcurrent warning limit. r/w word y l11 a y 20.0 0xda80 iout_cal_gain the iout_cal_gain command is used to set the resistance value of the current sense resistor in milliohms . (see also mfr_iout_cal_gain_tc). this command has two data bytes and is formatted in linear_5s_11s format. mfr_iout_cal_gain_tc the mfr_ iout_ cal_ gain_ tc command allows the user to program the temperature coefficient of the iout_ cal_ gain sense resistor or inductor dcr in ppm/c. this command has two data bytes and is formatted in 16-bit 2 s complement integer ppm. n = C32768 to 32767 ? 10 C6 . nominal temperature is 27c. the iout_cal_gain is multiplied by: [1.0 + mfr_iout_cal_gain_tc ? ( read_temperature_1 - 27)]. dcr sensing will have a typical value of 3900. the iout_cal_gain and mfr_iout_cal_gain_tc impact all current parameters including: read_iout, mfr_ read_iin_chan, iout_oc_fault_limit and iout_oc_warn_limit. ltc 3886 3886f 81 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails iout_oc_fault_limit the iout_oc_fault_limit command sets the value of the peak output current limit, in amperes. when the controller is in current limit, the overcurrent detector will indicate an overcurrent fault condition. the programmed overcurrent fault limit value is rounded up to the nearest one of the following set of discrete values: 25mv/iout_cal_gain low range (1.5x nominal loop gain) mfr_pwm_mode_ lt c 3886 [7]=0 28.6mv/iout_cal_gain 32.1mv/iout_cal_gain 35.7mv/iout_cal_gain 39.3mv/iout_cal_gain 42.9mv/iout_cal_gain 46.4mv/iout_cal_gain 50mv/iout_cal_gain 37.5mv/iout_cal_gain high range (nominal loop gain) mfr_pwm_mode_ lt c 3886 [7]=1 42.9mv/iout_cal_gain 48.2mv/iout_cal_gain 53.6mv/iout_cal_gain 58.9mv/iout_cal_gain 64.3mv/iout_cal_gain 69.6mv/iout_cal_gain 75mv/iout_cal_gain note: this is the peak of the current waveform. the read_iout command returns the average current. the peak output current limits are adjusted with temperature based on the mfr_iout_cal_gain_tc using the equation: peak current limit = iout_cal_gain ? (1 + mfr_iout_cal_gain_tc ? (read_temperture_1-27.0)). the ltpowerplay gui automatically convert the voltages to currents. the i out range is set with bit 7 of the mfr_pwm_mode_ lt c 3886 command. the iout_oc_fault_limit is ignored during ton_rise and toff_fall. if the iout_oc_fault_limit is exceeded, the device: ? sets the iout bit in the status word ? sets the iout overcurrent fault bit in the status_iout ? notifies the host by asserting alert, unless masked this command has two data bytes and is formatted in linear_5s_11s format. ltc 3886 3886f 82 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails iout_oc_warn_limit this command sets the value of the output current measured by the adc that causes an output overcurrent warning in amperes. the read_iout value will be used to determine if this limit has been exceeded. in response to the iout_oc_warn_limit being exceeded, the device: ? sets the none_of_the_above bit in the status_byte ? sets the iout bit in the status_word ? sets the iout overcurrent warning bit in the status_iout command, and ? notifies the host by asserting alert pin, unless masked the iout_oc_fault_limit is ignored during ton_rise and toff_fall. this command has two data bytes and is formatted in linear_5s_11s format input current and limits command name cmd code description type d ata format units eeprom default value mfr_iin_cal_gain 0xe8 the resistance value of the input current sense element in m. r/w word l11 m y 5.000 0xca80 mfr_iin_cal_gain the iout_cal_gain command is used to set the resistance value of the input current sense resistor in milliohms. (see also read_iin). this command has two data bytes and is formatted in linear_5s_11s format. command name cmd code description type paged d ata format units eeprom default value iin_oc_warn_limit 0x5d input overcurrent warning limit. r/w word n l11 a y 10.0 0xd280 iin_oc_warn_limit the iin_oc_warn_limit command sets the value of the input current measured by the adc, in amperes, that causes a warning indicating the input current is high. the read_iin value will be used to determine if this limit has been exceeded. in response to the iin_oc_warn_limit being exceeded, the device: ? sets the none_of_the_above bit in the status_byte ? sets the input bit in the upper byte of the status_word ? sets the iin overcurrent warning bit[1] in the status_input command, and ? notifies the host by asserting alert pin this command has two data bytes and is formatted in linear_5s_11s format. ltc 3886 3886f 83 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails t emperature external temperature calibration command name cmd code description type paged d ata format units eeprom default value mfr_temp_1_gain 0xf8 sets the slope of the external temperature sensor. r/w word y cf y 1.0 0x4000 mfr_temp_1_offset 0xf9 sets the offset of the external temperature sensor. r/w w ord y l11 c y 0.0 0x8000 mfr_temp_1_gain the mfr_temp_1_gain command will modify the slope of the external temperature sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor. this command has two data bytes and is formatted in 16-bit 2 s complement integer. the effective gain adjustment is n ? 2 C14 . the nominal value is 1. mfr_temp_1_offset the mfr_temp_1_offset command will modify the offset of the external temperature sensor to account for non- idealities in the element and errors associated with the remote sensing of the temperature in the inductor. this command has two data bytes and is formatted in linear_5s_11s format. external temperature limits command name cmd code description type paged d ata format units eeprom default value ot_fault_limit 0x4f external overtemperature fault limit. r/w word y l11 c y 100.0 0xeb20 ot_warn_limit 0x51 external overtemperature warning limit. r/w word y l11 c y 85.0 0xeaa8 ut_fault_limit 0x53 external undertemperature fault limit. r/w word y l11 c y C40.0 0xe580 ot_fault_limit the ot_fault_limit command sets the value of the external sense temperature measured by the adc, in degrees celsius, which causes an overtemperature fault. the read_temperature_1 value will be used to determine if this limit has been exceeded. this command has two data bytes and is formatted in linear_5s_11s format. ot_warn_limit the ot_warn_limit command sets the value of the external sense temperature measured by the adc, in degrees celsius, which causes an overtemperature warning. the read_temperature_1 value will be used to determine if this limit has been exceeded. ltc 3886 3886f 84 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails in response to the ot_warn_limit being exceeded, the device: ? sets the temperature bit in the status_byte ? sets the overtemperature warning bit in the status_temperature command, and ? notifies the host by asserting alert pin, unless masked this command has two data bytes and is formatted in linear_5s_11s format. ut_fault_limit the ut_ fault_ limit command sets the value of the external sense temperature measured by the adc, in degrees celsius, which causes an undertemperature fault. the read_ temperature_ 1 value will be used to determine if this limit has been exceeded. note : if the temp sensors are not installed, the ut_fault_limit can be set to C275 c and ut_fault_limit response set to ignore to avoid alert being asserted. this command has two data bytes and is formatted in linear_5s_11s format. t iming timingon sequence/ramp command name cmd code description type paged d ata format units eeprom default value ton_delay 0x60 time from run and/or operation on to output rail turn-on. r/w word y l11 ms y 0.0 0x8000 ton_rise 0x61 time from when the output starts to rise until the output voltage reaches the vout commanded value. r/w word y l11 ms y 8.0 0xd200 ton_max_fault_limit 0x62 maximum time from the start of ton_ rise for vout to cross the vout_uv_ fault_limit. r/w word y l11 ms y 10.0 0xd280 vout_transition_rate 0x27 rate the output changes when vout commanded to a new value. r/w word y l11 v/ms y 0.25 0xaa00 ton_delay the ton_delay command sets the time, in milliseconds, from when a start condition is received until the output voltage starts to rise. values from 0 ms to 83 seconds are valid. the resulting turn-on delay will have a typical delay of 270s for ton_delay = 0 and an uncertainty of 50s for all values of ton_delay. this command has two data bytes and is formatted in linear_5s_11s format. ton_rise the ton_rise command sets the time, in milliseconds, from the time the output starts to rise to the time the output enters the regulation band. values from 0 to 1.3 seconds are valid. the part will be in discontinuous mode during ton_rise events. if ton_rise is less than 0.25 ms, the ltc3886 digital slope will be bypassed and the output voltage transition will only be controlled by the analog performance of the pwm switcher. the number of steps in ton_rise is equal to ton_rise (in ms)/0.1ms with an uncertainty of 0.1ms. this command has two data bytes and is formatted in linear_5s_11s format. ltc 3886 3886f 85 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails ton_max_fault_limit the ton_max_fault_limit command sets the value, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit, or output overcurrent limit. a data value of 0 ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. the maximum limit is 83 seconds. this command has two data bytes and is formatted in linear_5s_11s format. vout_transition_rate when a pmbus device receives either a vout_command or operation ( margin high, margin low) that causes the output voltage to change this command set the rate in v/ms at which the output voltage changes. this commanded rate of change does not apply when the unit is commanded on or off. the maximum allowed slope is 4v/ms. this command has two data bytes and is formatted in linear_5s_11s format. timingoff sequence/ramp command name cmd code description type paged d ata format units eeprom default value toff_delay 0x64 time from run and/or operation off to the start of toff_fall ramp. r/w word y l11 ms y 0.0 0x8000 toff_fall 0x65 t ime from when the output starts to fall until the output reaches zero volts. r/w word y l11 ms y 8.0 0xd200 toff_max_warn_limit 0x66 maximum allowed time, after toff_f all completed, for the unit to decay below 12.5%. r/w word y l11 ms y 150 0xf258 toff_delay the toff_delay command sets the time, in milliseconds, from when a stop condition is received until the output voltage starts to fall. values from 0 to 83 seconds are valid. the resulting turn off delay will have a typical delay of 270s for toff_delay = 0 and an uncertainty of 50 s for all values of toff_delay. toff_delay is not applied when a fault event occurs this command has two data bytes and is formatted in linear_5s_11s format. toff_fall the toff_fall command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt - age is commanded to zero. it is the ramp time of the v out dac. when the v out dac is zero, the pwm output will be set to high impedance state. the part will maintain the mode of operation programmed. for defined toff_fall times, the user should set the part to continuous conduction mode. loading the max value indicates the part will ramp down at the slowest possible rate. the minimum supported fall time is 0.25 ms. a value less than 0.25 ms will result in a 0.25 ms ramp. the maximum fall time is 1.3 seconds. the number of steps in toff_fall is equal to toff_fall ( in ms)/0.1ms with an uncertainty of 0.1ms. in discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current. this command has two data bytes and is formatted in linear_5s_11s format. ltc 3886 3886f 86 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails toff_max_warn_limit the toff_max_warn_limit command sets the value, in milliseconds, on how long the unit can attempt to turn off the output until a warning is asserted. the output is considered off when the v out voltage is less than 12.5% of the programmed vout_command value. the calculation begins after toff_fall is complete. a data value of 0 ms means that there is no limit and that the unit can attempt to turn off the output voltage indefinitely. other than 0, values from 120ms to 524 seconds are valid. this command has two data bytes and is formatted in linear_5s_11s format. precondition for restart command name cmd code description type paged d ata format units eeprom default value mfr_restart_ delay 0xdc minimum time the run pin is held low by the ltc3886. r/w word y l11 ms y 500 0xfbe8 mfr_restart_delay this command specifies the minimum run off time in milliseconds. this device will pull the run pin low for this length of time once a falling edge of run has been detected. the minimum recommended value is 136ms. note: the restart delay is different than the retry delay. the restart delay pulls run low for the specified time, after which a standard start-up sequence is initiated. the minimum restart delay should be equal to toff_delay + toff_ fall + 136 ms. valid values are from 136 ms to 65.52 seconds in 16 ms increments. to assure a minimum off time, set the mfr_restart_delay 16 ms longer than the desired time. the output rail can be off longer than the mfr_ restart_delay after the run pin is pulled high if the output decay bit 0 is enabled in mfr_chan_config_ lt c 3886 and the output takes a long time to decay below 12.5% of the programmed value. this command has two data bytes and is formatted in linear_5s_11s format . f ault r esponse fault responses all faults command name cmd code description type paged d ata format units eeprom default value mfr_retry_ delay 0xdb retry interval during fault retry mode. r/w word y l11 ms y 350 0xfabc mfr_retry_delay this command sets the time in milliseconds between retries if the fault response is to retry the controller at specified intervals. this command value is used for all fault responses that require retry. the retry time starts once the fault has been detected by the offending channel. valid values are from 120ms to 83.88 seconds in 10s increments. note: the retry delay time is determined by the longer of the mfr_retry_delay command or the time required for the regulated output to decay below 12.5% of the programmed value. if the natural decay time of the output is too long, it is possible to remove the voltage requirement of the mfr_retry_delay command by asserting bit 0 of mfr_chan_config_ lt c 3886. this command has two data bytes and is formatted in linear_5s_11s format. ltc 3886 3886f 87 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails fault responses input voltage command name cmd code description type paged d ata format units eeprom default value vin_ov_fault_response 0x56 action to be taken by the device when an input supply overvoltage fault is detected. r/w byte y reg y 0x80 vin_ov_fault_response the vin_ov_fault_response command instructs the device on what action to take in response to an input over- voltage fault. the data byte is in the format given in table 11. the device also: ? sets the none_of_the_above bit in the status_byte ? set the input bit in the upper byte of the status_word ? sets the vin overvoltage fault bit in the status_input command, and ? notifies the host by asserting alert pin, unless masked this command has one data byte. fault responses output voltage command name cmd code description type paged d ata format units eeprom default value vout_ov_fault_response 0x41 action to be taken by the device when an output overvoltage fault is detected. r/w byte y reg y 0xb8 vout_uv_fault_response 0x45 action to be taken by the device when an output undervoltage fault is detected. r/w byte y reg y 0xb8 ton_max_fault_ response 0x63 action to be taken by the device when a ton_max_fault event is detected. r/w byte y reg y 0xb8 vout_ov_fault_response the vout_ov_fault_response command instructs the device on what action to take in response to an output overvoltage fault. the data byte is in the format given in table 7. the device also: ? sets the vout_ov bit in the status_byte ? sets the vout bit in the status_word ? sets the vout overvoltage fault bit in the status_vout command ? notifies the host by asserting alert pin, unless masked the only values recognized for this command are: 0x00Cpart performs ov pull down only, or ov_pulldown. 0x80Cthe device shuts down ( disables the output) and the unit does not attempt to retry. ( pmbus, part ii, section 10.7). 0xb8Cthe device shuts down ( disables the output) and device attempts to retry continuously, without limitation, until it is commanded off ( by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. ltc 3886 3886f 88 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails 0x4n the device shuts down and the unit does not attempt to retry. the output remains disabled until the part is com- manded off then on or the run pin is asserted low then high or reset through the command or removal of vin. the ov fault must remain active for a period of n ? 10 s, where n is a value from 0 to 7. 0x78+n the device shuts down and the unit attempts to retry continuously until either the fault condition is cleared or the part is commanded off then on or the run pin is asserted low then high or reset through the command or removal of vin. the ov fault must remain active for a period of n ? 10s, where n is a value from 0 to 7. any other value will result in a cml fault and the write will be ignored. this command has one data byte. table 7. vout_ov_fault_response data byte contents bits description value meaning 7:6 response for all values of bits [7:6], the ltc3886: ? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command. ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltc3886. 00 part performs ov pull down only or ov_pulldown (i.e., turns off the top mosfet and turns on lower mosfet while v out is > vout_ov_fault). 01 the pmbus device continues operation for the delay time specified by bits [2:0] and the delay time unit specified for that particular fault. if the fault condition is still present at the end of the delay time, the unit responds as programmed in the retry setting (bits [5:3]). 10 the device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 not supported. writing this value will generate a cml fault. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared until the device is commanded off bias power is removed. 111 the pmbus device attempts to restart continuously, without limitation, until it is commanded off (by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. note: the retry interval is set by the mfr_retry_dela y command. 2:0 delay time 000-111 the delay time in 10s increments. this delay time determines how long the controller continues operating after a fault is detected. only valid for deglitched off state. vout_uv_fault_response the vout_uv_fault_response command instructs the device on what action to take in response to an output undervoltage fault. the data byte is in the format given in table 8. the device also: ? sets the none_of_the_above bit in the status_byte ? sets the vout bit in the status_word ? sets the vout undervoltage fault bit in the status_vout command ? notifies the host by asserting alert pin, unless masked ltc 3886 3886f 89 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails the uv fault and warn are masked until the following criteria are achieved: 1) the ton_max_fault_limit has been reached 2) the ton_delay sequence has completed 3) the ton_rise sequence has completed 4) the vout_uv_fault_limit threshold has been reached 5) the iout_oc_fault_limit is not present the uv fault and warn are masked whenever the channel is not active. the uv fault and warn are masked during ton_rise and toff_fall sequencing. this command has one data byte. table 8. vout_uv_fault_response data byte contents bits description value meaning 7:6 response for all values of bits [7:6], the ltc3886: ? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command. ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? the device receives a restore_user_all command. ? the device receives a mfr_reset command. ? the device supply power is cycled. 00 the pmbus device continues operation without interruption. (ignores the fault functionally) 01 the pmbus device continues operation for the delay time specified by bits [2:0] and the delay time unit specified for that particular fault. if the fault condition is still present at the end of the delay time, the unit responds as programmed in the retry setting (bits [5:3]). 10 the device shuts down (disables the output) and responds according to the retry setting in bits [5:3]. 11 not supported. writing this value will generate a cml fault. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared until the device is commanded off bias power is removed. 111 the pmbus device attempts to restart continuously, without limitation, until it is commanded off (by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. note: the retry interval is set by the mfr_retry_dela y command. 2:0 delay time 000-111 the delay time in 10s increments. this delay time determines how long the controller continues operating after a fault is detected. only valid for deglitched off state. ltc 3886 3886f 90 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails ton_max_fault_response the ton_max_fault_response command instructs the device on what action to take in response to a ton_max fault. the data byte is in the format given in table 11. the device also: ? sets the none_of_the_above bit in the status_byte ? sets the vout bit in the status_word ? sets the ton_max_fault bit in the status_vout command, and ? notifies the host by asserting alert pin, unless masked a value of 0 disables the ton_max_fault_response. it is not recommended to use 0. this command has one data byte. fault responses output current command name cmd code description type paged d ata format units eeprom default value iout_oc_fault_response 0x47 action to be taken by the device when an output overcurrent fault is detected. r/w byte y reg y 0x00 iout_oc_fault_response the iout_oc_fault_response command instructs the device on what action to take in response to an output overcurrent fault. the data byte is in the format given in table 9. the device also: ? sets the none_of_the_above bit in the status_byte ? sets the iout_oc bit in the status_byte ? sets the iout bit in the status_word ? sets the iout overcurrent fault bit in the status_iout command, and ? notifies the host by asserting alert pin, unless masked this command has one data byte. ltc 3886 3886f 91 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails table 9. iout_oc_fault_response data byte contents bits description value meaning 7:6 response for all values of bits [7:6], the ltc3886: ? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command. ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? the device receives a restore_user_all command. ? the device receives a mfr_reset command. ? the device supply power is cycled. 00 the ltc3886 continues to operate indefinitely while maintaining the output current at the value set by iout_oc_fault_limit without regard to the output voltage (known as constant- current or brick-wall limiting). 01 not supported. 10 the ltc3886 continues to operate, maintaining the output current at the value set by iout_oc_fault_limit without regard to the output voltage, for the delay time set by bits [2:0]. if the device is still operating in current limit at the end of the delay time, the device responds as programmed by the retry setting in bits [5:3]. 11 the ltc3886 shuts down immediately and responds as programmed by the retr y setting in bits [5:3]. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared by cycling the run pin or removing bias power. 111 the device attempts to restart continuously, without limitation, until it is commanded off (by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. note: the retry interval is set by the mfr_retry_delay command. 2:0 delay time 000-111 the number of delay time units in 16ms increments. this delay time is used to determine the amount of time a unit is to continue operating after a fault is detected before shutting down. only valid for deglitched off response. fault responses ic temperature command name cmd code description type paged d ata format units eeprom default value mfr_ot_fault_ response 0xd6 action to be taken by the device when an internal overtemperature fault is detected. r byte n reg 0xc0 mfr_ot_fault_response the mfr_ot_fault_response command byte instructs the device on what action to take in response to an internal overtemperature fault. the data byte is in the format given in table 10. the ltc3886 also: ? sets the none_of_the_above bit in the status_byte ? sets the mfr bit in the status_word, and ? sets the overtemperature fault bit in the status_mfr_specific command ? notifies the host by asserting alert pin, unless masked this command has one data byte. ltc 3886 3886f 92 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails table 10. data byte contents mfr_ot_fault_response bits description value meaning 7:6 response for all values of bits [7:6], the ltc3886: ? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command. ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltc3886. 00 not supported. writing this value will generate a cml fault. 01 not supported. writing this value will generate a cml fault 10 the device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 the devices output is disabled while the fault is present. operation resumes and the output is enabled when the fault condition no longer exists. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared. 001-111 not supported. writing this value will generate cml fault. 2:0 delay time xxx not supported . value ignored fault responses external temperature command name cmd code description type paged d ata format units eeprom default value ot_fault_ response 0x50 action to be taken by the device when an external overtemperature fault is detected, r/w byte y reg y 0xb8 ut_fault_ response 0x54 action to be taken by the device when an external undertemperature fault is detected. r/w byte y reg y 0xb8 ot_fault_response the ot_fault_response command instructs the device on what action to take in response to an external overtem- perature fault on the external temp sensors. the data byte is in the format given in table 11. the device also: ? sets the temperature bit in the status_by te ? sets the overtemperature fault bit in the status_temperature command, and ? notifies the host by asserting alert pin, unless masked this command has one data byte. ut_fault_response the ut_fault_response command instructs the device on what action to take in response to an external under - temperature fault on the external temp sensors. the data byte is in the format given in table 11. the device also: ? sets the temperature bit in the status_by te ? sets the undertemperature fault bit in the status_temperature command, and ? notifies the host by asserting alert pin , unless masked ltc 3886 3886f 93 for more information www.linear.com/ltc3886 this condition is detected by the adc so the response time may be up to 100ms. this command has one data byte. table 11. data byte contents: ton_max_fault_response, vin_ov_fault_response, ot_fault_response, ut_fault_response bits description value meaning 7:6 response for all values of bits [7:6], the ltc3886: ? sets the corresponding fault bit in the status commands, and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command. ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? the device receives a restore_user_all command. ? the device receives a mfr_reset command. ? the device supply power is cycled. 00 the pmbus device continues operation without interruption. 01 not supported. writing this value will generate a cml fault. 10 the device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 not supported. writing this value will generate a cml fault. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared until the device is commanded off bias power is removed. 111 the pmbus device attempts to restart continuously, without limitation, until it is commanded off (by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. note: the retry interval is set by the mfr_retry_delay command. 2:0 delay t ime xxx not supported. values ignored f ault s haring fault sharing propagation command name cmd code description type paged d ata format units eeprom default value mfr_fault_ propagate_ lt c 3886 0xd2 configuration that determines which faults are propagated to the fault pins. r/w word y reg y 0x6993 mfr_fault_propagate_ ltc 3886 the mfr_fault_propagate_ lt c 3886 command enables the faults that can cause the fault n pin to assert low. the command is formatted as shown in table 12. faults can only be propagated to the fault n pin if they are programmed to respond to faults. this command has two data bytes. p m b us c o mm an d de t ails ltc 3886 3886f 94 for more information www.linear.com/ltc3886 table 12: fault n propagate fault configuration the fau lt0 and fau lt1 pins are designed to provide electrical notification of selected events to the user. some of these events are common to both output channels. others are specific to an output channel. they can also be used to share faults between channels. bit(s) symbol operation b[15] vout disabled while not decayed. this is used in a polyphase configuration when bit 0 of the mfr_chan_config_ lt c 3886 is a zero. if the channel is turned off, by toggling the run pin or commanding the part off, and then the run is reasserted or the part is commanded back on before the output has decayed, vout will not restart until the 12.5% decay is honored. the fault pin is asserted during this condition if bit 15 is asserted. b[14] mfr_fault_propagate_short_cmd_ cycle 0: no action 1: asserts low if commanded off then on before the output has sequenced off. re-asserts high 120ms after sequence off. b[13] mfr_fault_propagate_ton_max_fault 0: no action if a ton_max_fault fault is asserted 1: associated output will be asserted low if a ton_max_fault fault is asserted fault0 is associated with page 0 ton_max_fault faults fault1 is associated with page 1 ton_max_fault faults b[12] reserved must be 0 b[11] mfr_fault0_propagate_int_ot, mfr_fault1_propagate_int_ot 0: no action if the mfr_ot_fault_limit fault is asserted 1: associated output will be asserted low if the mfr_ot_fault_limit fault is asserted b[10] reser ved must be 0 b[9] reserved must be 0 b[8] mfr_fault0_propagate_ut, mfr_fault1_propagate_ut 0: no action if the ut_fault_limit fault is asserted 1: associated output will be asserted low if the ut_fault_limit fault is asserted fau lt0 is associated with page 0 ut faults fau lt1 is associated with page 1 ut faults b[7] mfr_fault0_propagate_ot, mfr_fault1_propagate_ot 0: no action if the ot_fault_limit fault is asserted 1: associated output will be asserted low if the ot_fault_limit fault is asserted fau lt0 is associated with page 0 ot faults fau lt1 is associated with page 1 ot faults b[6] reserved b[5] reserved b[4] mfr_fault0_propagate_input_ov, mfr_fault1_propagate_input_ov 0: no action if the vin_ov_fault_limit fault is asserted 1: associated output will be asserted low if the vin_ov_fault_limit fault is asserted b[3] reserved b[2] mfr_fault0_propagate_iout_oc, mfr_fault1_propagate_iout_oc 0: no action if the iout_oc_fault_limit fault is asserted 1: associated output will be asserted low if the iout_oc_fault_limit fault is asserted fau lt0 is associated with page 0 oc faults fau lt1 is associated with page 1 oc faults b[1] mfr_fault0_propagate_vout_uv, mfr_fault1_propagate_vout_uv 0: no action if the vout_uv_fault_limit fault is asserted 1: associated output will be asserted low if the vout_uv_fault_limit fault is asserted fa u lt0 is associated with page 0 uv faults fau lt1 is associated with page 1 uv faults b[0] mfr_fault0_propagate_vout_ov, mfr_fault1_propagate_vout_ov 0: no action if the vout_ov_fault_limit fault is asserted 1: associated output will be asserted low if the vout_ov_fault_limit fault is asserted fau lt0 is associated with page 0 ov faults fau lt1 is associated with page 1 ov faults p m b us c o mm an d de t ails ltc 3886 3886f 95 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails fault sharing response command name cmd code description type paged d ata format units eeprom default value mfr_fault_response 0xd5 action to be taken by the device when the fault pin is asserted low. r/w byte y reg y 0xc0 mfr_fault_response the mfr_fault_response command instructs the device on what action to take in response to the fault n pin being pulled low by an external source. supported values: value meaning 0xc0 fault_inhibit the ltc3886 will three-state the output in response to the fault pin pulled low. 0x00 fault_ignore the ltc3886 continues operation without interruption. the device also: ? sets the mfr bit in the status_word. ? sets bit 0 in the status_mfr_specific command to indicate faul tn is being pulled low ? notifies the host by asserting alert , unless masked this command has one data byte. s cratchpad command name cmd code description type paged d ata format units eeprom default value user_data_00 0xb0 oem reserved. typically used for part serialization. r/w word n reg y na user_data_01 0xb1 manufacturer reserved for ltpowerplay. r/w word y reg y na user_data_02 0xb2 oem reserved. typically used for part serialization. r/w word n reg y na user_data_03 0xb3 a eeprom word available for the user. r/w word y reg y 0x0000 user_data_04 0xb4 a eeprom word available for the user. r/w word n reg y 0x0000 user_data_00 through user_data_04 these commands are non-volatile memory locations for customer storage. the customer has the option to write any value to the user_data_nn at any time. however, the ltpowerplay software and contract manufacturers use some of these commands for inventory control. modifying the reserved user_data_nn commands may lead to undesirable inventory control and incompatibility with these products. these commands have 2 data bytes and are in register format. ltc 3886 3886f 96 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails i dentification command name cmd code description type paged d ata format units eeprom default value pmbus_revision 0x98 pmbus revision supported by this device. current revision is 1.2. r byte n reg fs 0x22 capability 0x19 summary of pmbus optional communication protocols supported by this device. r byte n reg 0xb0 mfr_id 0x99 the manufacturer id of the ltc3886 in ascii. r string n asc lt c mfr_model 0x9a manufacturer part number in ascii. r string n asc ltc3886 mfr_special_id 0xe7 manufacturer code representing the ltc3886. r word n reg 0x460x pmbus_revision the pmbus_revision command indicates the revision of the pmbus to which the device is compliant. the ltc3886 is pmbus version 1.2 compliant in both part i and part ii. this read-only command has one data byte. capability this command provides a way for a host system to determine some key capabilities of a pmbus device. the ltc3886 supports packet error checking, 400khz bus speeds, and alert pin. this read-only command has one data byte. mfr_id the mfr_id command indicates the manufacturer id of the ltc3886 using ascii characters. this read-only command is in block format. mfr_model the mfr_model command indicates the manufacturers part number of the ltc3886 using ascii characters. this read-only command is in block format. mfr_special_id the 16- bit word representing the part name and revision . 0 x46 denotes the part is an ltc3886, xx is adjustable by the manufacturer. this read-only command has two data bytes. ltc 3886 3886f 97 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails f ault w arning and s tatus command name cmd code description type paged format units eeprom default value clear_faults 0x03 clear any fault bits that have been set. send byte n na smbalert_mask 0x1b mask activity. block r/w y reg y see cmd details mfr_clear_peaks 0xe3 clears all peak values. send byte n na status_byte 0x78 one byte summary of the units fault condition. r/w byte y reg na status_word 0x79 tw o byte summary of the units fault condition. r/w word y reg na status_vout 0x7a output voltage fault and warning status. r/w byte y reg na status_iout 0x7b output current fault and warning status. r/w byte y reg na status_input 0x7c input supply fault and warning status. r/w byte n reg na status_ temperature 0x7d external temperature fault and warning status for read_temerature_1. r/w byte y reg na status_cml 0x7e communication and memory fault and warning status. r/w byte n reg na status_mfr_ specific 0x80 manufacturer specific fault and state information. r/w byte y reg na mfr_pads 0xe5 digital status of the i/o pads. r word n reg na mfr_common 0xef manufacturer status bits that are common across multiple lt c chips. r byte n reg na clear_faults the clear_faults command is used to clear any fault bits that have been set. this command clears all bits in all status commands simultaneously. at the same time, the device negates ( clears, releases) its alert pin signal output if the device is asserting the alert pin signal. if the fault is still present when the bit is cleared, the fault bit will remain set and the host notified by asserting the alert pin low. clear_faults can take up to 10 s to process. if a fault occurs within that time frame it may be cleared before the status register is set. this write-only command has no data bytes. the clear_faults does not cause a unit that has latched off for a fault condition to restart. units that have shut down for a fault condition are restarted when: ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? mfr_reset command is issued. ? bias power is removed and reapplied to the integrated circuit smbalert_mask the smbalert_mask command can be used to prevent a particular status bit or bits from asserting alert as they are asserted. ltc 3886 3886f 98 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails figure 47 shows an example of the write word format used to set an alert mask, in this case without pec. the bits in the mask byte align with bits in the specified status register. for example, if the status_temperature command code is sent in the first data byte, and the mask byte contains 0 x40, then a subsequent external overtemperature warning would still set bit 6 of status_temperature but not assert alert . all other supported status_temperature bits would continue to assert alert if set. figure 48 shows an example of the block write C block read process call protocol used to read back the present state of any supported status register, again without pec. smbalert_mask cannot be applied to status_byte, status_word, mfr_common or mfr_pads_ltc3886. factory default masking for applicable status registers is shown below. providing an unsupported command code to smbalert_mask will generate a cml for invalid/unsupported data. smbalert_mask default setting: (refer also to figure 2) status resister alert mask value masked bits status_vout 0x00 none status_iout 0x00 none status_temperature 0x00 none slave address smbalert_mask command code block count (= 1) w a a s 7 8 8 1 status_x command code 8 1 1 1 1 1 a a ? sr 1 block count (= 1) a na p 3886 f45 a 8 8 1 1 1 1 mask byte slave address 7 r 1 p 1 slave address smbalert_mask command code status_x command code w a a s 7 8 8 1 8 1 1 1 1 1 a a mask byte 3886 f44 figure 47. example of setting smbalert_mask figure 48. example of reading smbalert_mask status_cml 0x00 none status_input 0x00 none status_mfr_specific 0x11 bit 4 (internal pll unlocked), bit 0 ( fault pulled low by external device) mfr_clear_peaks the mfr_clear_peaks command clears the mfr_*_peak data values. a mfr_reset command will also clear the mfr_*_peak data values. this write-only command has no data bytes. status_byte the status_byte command returns one byte of information with a summary of the most critical faults. this is the lower byte of the status word. ltc 3886 3886f 99 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails status_byte message contents: bit status bit name meaning 7* busy a fault was declared because the ltc3886 was unable to respond. 6 off this bit is set if the channel is not providing power to its output, regardless of the reason, including simply not being enabled. 5 vout_ov an output overvoltage fault has occurred. 4 iout_oc an output overcurrent fault has occurred. 3 vin_uv not supported (ltc3886 returns 0). 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory or logic fault has occurred. 0* none of the above a fault not listed in bits[7:1] has occurred. * alert can be asserted if either of these bits is set. they may be cleared by writing a 1 to their bit position in the status_ byte, in lieu of a clear_ faults command. this command has one data byte. status_word the status_word command returns a two-byte summary of the channel's fault condition. the low byte of the status_word is the same as the status_byte command. status_word high byte message contents: bit status bit name meaning 15 v out an output voltage fault or warning has occurred. 14 i out an output current fault or warning has occurred. 13 input an input voltage fault or warning has occurred. 12 mfr_specific a fault or warning specific to the ltc3886 has occurred. 11 power_good# the power_good state is false if this bit is set. 10 fans not supported (ltc3886 returns 0). 9 other not supported (ltc3886 returns 0). 8 unknown not supported (ltc3886 returns 0). if any of the bits in the upper byte are set, none_of_the_above is asserted. this command has two data bytes. status_vout the status_vout command returns one byte of v out status information. status_vout message contents: bit meaning 7 v out overvoltage fault. 6 v out overvoltage warning. 5 v out undervoltage warning. 4 v out undervoltage fault. 3 v out max warning. 2 ton max fault. 1 toff max fault. 0 not supported (ltc3886 returns 0). ltc 3886 3886f 100 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. any supported fault bit in this command will initiate an alert event. this command has one data byte. status_iout the status_iout command returns one byte of i out status information. status_iout message contents: bit meaning 7 i out overcurrent fault. 6 not supported (ltc3886 returns 0). 5 i out overcurrent warning. 4:0 not supported (ltc3886 returns 0). the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. any supported fault bit in this command will initiate an alert event. this command has one data byte. status_input the status_input command returns one byte of v in (vinsns) status information. status_input message contents: bit meaning 7 v in overvoltage fault. 6 not supported (ltc3886 returns 0). 5 v in undervoltage warning. 4 not supported (ltc3886 returns 0). 3 unit off for insufficient v in . 2 not supported (ltc3886 returns 0). 1 i in overcurrent warning. 0 not supported (ltc3886 returns 0). the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. any supported fault bit in this command will initiate an alert event. bit 3 of this command is not latched and will not generate an alert even if it is set. this command has one data byte. ltc 3886 3886f 101 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails status_temperature the status_temperature commands returns one byte with status information on temperature. this is a paged command and is related to the respective read_temperature_1 value. status_temperature message contents: bit meaning 7 external overtemperature fault. 6 external overtemperature warning. 5 not supported (ltc3886 returns 0). 4 external undertemperature fault. 3:0 not supported (ltc3886 returns 0). . the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. this command has one data byte. status_cml the status_cml command returns one byte of status information on received commands, internal memory and logic. status_cml message contents: bit meaning 7 invalid or unsupported command received. 6 invalid or unsupported data received. 5 packet error check failed. 4 memory fault detected. 3 processor fault detected. 2 reserved (ltc3886 returns 0). 1 other communication fault. 0 other memory or logic fault. if either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. continued operation of the part is not recommended if these bits are continuously set. the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. any supported fault bit in this command will initiate an alert event. this command has one data byte. ltc 3886 3886f 102 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails status_mfr_specific the status_mfr_specific commands returns one byte with the manufacturer specific status information. the format for this byte is: bit meaning 7 internal temperature fault limit exceeded. 6 internal temperature warn limit exceeded. 5 factory trim area eeprom crc fault. 4 pll is unlocked 3 fault log present 2 v dd33 uv or ov fault 0 fault pin asserted low by external device if any of these bits are set, the mfr bit in the status_word will be set, and alert may be asserted. the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. however, the fault log present bit can only be cleared by issuing the mfr_fault_log_clear command. any supported fault bit in this command will initiate an alert event. this command has one data byte. mfr_pads this command provides the user a means of directly reading the digital status of the i/o pins of the device. the bit assignments of this command are as follows: bit assigned digital pin 15 v dd33 ov fault 14 v dd33 uv fault 13 reserved 12 reserved 11 adc values invalid, occurs during start-up. may occur briefly on current measurement channels during normal operation 10 sync clocked by external device (when ltc3886 configured to drive sync pin) 9 channel 1 power good 8 channel 0 power good 7 ltc3886 driving run1 low 6 ltc3886 driving run0 low 5 run1 pin state 4 run0 pin state 3 ltc3886 driving fau lt1 low 2 ltc3886 driving fau lt0 low 1 fau lt1 pin state 0 fau lt0 pin state a 1 indicates the condition is true. this read-only command has two data bytes. ltc 3886 3886f 103 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails mfr_common the mfr_common command contains bits that are common to all lt c digital power and telemetry products. bit meaning 7 chip not driving alert low 6 ltc3886 not busy 5 calculations not pending 4 ltc3886 outputs not in transition 3 eeprom initialized 2 reserved 1 share_clk timeout 0 wp pin status this read-only command has one data byte. t elemetry command name cmd code description type paged format units eeprom default value read_vin 0x88 measured input supply voltage. r word n l11 v na read_iin 0x89 measured input supply current. r word n l11 a na read_vout 0x8b measured output voltage. r word y l16 v na read_iout 0x8c measured output current. r word y l11 a na read_temperature_1 0x8d external diode junction temperature. this is the value used for all temperature related processing, including iout_cal_gain. r word y l11 c na read_temperature_2 0x8e internal junction temperature. does not affect any other commands. r word n l11 c na read_frequency 0x95 measured pwm switching frequency. r word y l11 khz na read_pout 0x96 calculated output power. r word y l11 w na read_pin 0x97 calculated input power. r word n l11 w na mfr_iout_peak 0xd7 report the maximum measured value of read_iout since last mfr_clear_peaks. r word y l11 a na mfr_adc_control 0xd8 adc telemetry parameter selected for repeated fast adc read back r/w byte n reg 0x00 mfr_vout_peak 0xdd maximum measured value of read_vout since last mfr_clear_peaks. r word y l16 v na mfr_vin_peak 0xde maximum measured value of read_vin since last mfr_clear_peaks. r word n l11 v na mfr_temperature_1_peak 0xdf maximum measured value of external temperature (read_temperature_1) since last mfr_clear_peaks. r word y l11 c na mfr_read_iin_peak 0xe1 maximum measured value of read_iin command since last mfr_clear_peaks. r word n l11 a na mfr_read_ichip 0xe4 measured current used by the ltc3886. r word n l11 a na mfr_temperature_2_peak 0xf4 peak internal die temperature since last mfr_clear_peaks. r word n l11 c na ltc 3886 3886f 104 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails read_vin the read_vin command returns the measured v in pin voltage, in volts added to read_ichip ? mfr_rvin. this compensates for the ir voltage drop across the v in filter element due to the supply current of the ltc3886. this read-only command has two data bytes and is formatted in linear_5s_11s format. read_vout the read_vout command returns the measured output voltage in the same format as set by the vout_mode command. this read-only command has two data bytes and is formatted in linear_16u format. read_iin the read_iin command returns the input current, in amperes, as measured across the input current sense resistor (see also mfr_iin_cal_gain). this read-only command has two data bytes and is formatted in linear_5s_11s format. read_iout the read_iout command returns the average output current in amperes. the iout value is a function of: a) the differential voltage measured across the i sense pins b) the iout_cal_gain value c) the mfr_iout_cal_gain_tc value, and d) read_temperature_1 value e) the mfr_temp_1_gain and the mfr_temp_1_offset this read-only command has two data bytes and is formatted in linear_5s_11s format. read_temperature_1 the read_temperature_1 command returns the temperature, in degrees celsius, of the external sense element. this read-only command has two data bytes and is formatted in linear_5s_11s format. read_temperature_2 the read_temperature_2 command returns the ltc3886s die temperature, in degrees celsius, of the internal sense element. this read-only command has two data bytes and is formatted in linear_5s_11s format. read_frequency the read_frequency command is a reading of the pwm switching frequency in khz. this read-only command has 2 data bytes and is formatted in linear_5s_11s format. read_pout the read_pout command is a reading of the dc/dc converter output power in watts. pout is calculated based on the most recent correlated output voltage and current reading. this read-only command has 2 data bytes and is formatted in linear_5s_11s format. ltc 3886 3886f 105 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails read_pin the read_pin command is a reading of the dc/dc converter input power in watts. pin is calculated based on the most recent input voltage and current reading. this read-only command has 2 data bytes and is formatted in linear_5s_11s format. mfr_iout_peak the mfr_ iout_ peak command reports the highest current, in amperes, reported by the read_ iout measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_adc_control the mfr_adc_control command determines the adc read back selection. a default value of 0 in the command runs the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of 100ms. the user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms. this command has a latency of up to 2 adc conversions or approximately 16ms ( external temperature conversions may have a latency of up to 3 adc conversion or approximately 24 ms). it is recommended the part remain in standard telemetry mode except for special cases where fast adc updates of a single parameter is required. the part should be commanded to monitor the desired parameter for a limited period of time ( less then 1 second) then set the command back to standard round robin mode. if this command is set to any value except standard round robin telemetry (0) all warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage servoing is disabled. when round robin is reasserted, all warnings and faults and servo mode are re-enabled. commanded value telemetry command name description 0x0f reserved 0x0e reserved 0x0d reserved 0x0c read_temperature_1 channel 1 external temperature 0x0b reserved 0x0a read_iout channel 1 measured output current 0x09 read_vout channel 1 measured output voltage 0x08 read_temperature_1 channel 0 external temperature 0x07 reserved 0x06 read_iout channel 0 measured output current 0x05 read_vout channel 0 measured output voltage 0x04 read_temperature_2 internal junction temperature 0x03 read_iin measured input supply current 0x02 mfr_read_ichip measured supply current of the ltc3886 0x01 read_vin measured input supply voltage 0x00 standard adc round robin telemetry if a reserved command value is entered, the telemetry will default to internal ic temperature and issue a cml fault. cml faults will continue to be issued by the ltc3886 until a valid command value is entered. the accuracy of the measured input supply voltage is only guaranteed if the mfr_adc_control command is set to standard round robin telemetry. this write-only command has 1 data byte and is formatted in register format. ltc 3886 3886f 106 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails mfr_vout_peak the mfr_vout_peak command reports the highest voltage, in volts, reported by the read_vout measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_16u format. mfr_vin_peak the mfr_vin_peak command reports the highest voltage, in volts, reported by the read_vin measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_temperature_1_peak the mfr_temperature_1_peak command reports the highest temperature, in degrees celsius, reported by the read_temperature_1 measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_read_iin_peak the mfr_read_iin_peak command reports the highest current, in amperes, reported by the read_iin measurement. this command is cleared using the mfr_clear_peaks command. this command has two data bytes and is formatted in linear_5s_11s format. mfr_read_ichip the mfr_read_ichip command returns the measured input current, in amperes, used by the ltc3886. this command has two data bytes and is formatted in linear_5s_11s format. mfr_temperature_2_peak the mfr_temperature_2_peak command reports the highest temperature, in degrees celsius, reported by the read_temperature_2 measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. eeprom m emory c ommands store/restore command name cmd code description type paged format units eeprom default value store_user_all 0x15 store user operating memory to eeprom. send byte n na restore_user_all 0x16 restore user operating memory from eeprom. send byte n na mfr_compare_user_all 0xf0 compares current command contents with eeprom. send byte n na ltc 3886 3886f 107 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails store_user_all the store_user_all command instructs the pmbus device to copy the non-volatile user contents of the operating memory to the matching locations in the non-volatile user eeprom memory. executing this command if the die temperature exceeds 85 c or is below 0 c is not recommended and the data retention of 10 years cannot be guaranteed. if the die temperature exceeds 130 c, the store_user_all command is disabled. the command is re-enabled when the ic temperature drops below 125c. communication with the ltc3886 and programming of the eeprom can be initiated when vdd33 is available and vin is not applied. to enable the part in this state, using global address 0 x5b write mfr_ee_unlock to 0 x2b followed by 0xc4. the ltc3886 will now communicate normally, and the project file can be updated. to write the updated project file to the eeprom issue a store_user_all command. when vin is applied, a mfr_reset must be issued to allow the pwm to be enabled and valid adcs to be read. this write-only command has no data bytes. restore_user_all the restore_user_all command instructs the pmbus device to copy the contents of the non-volatile user memory to the matching locations in the operating memory. the values in the operating memory are overwritten by the value retrieved from the user commands. the ltc3886 ensures both channels are off, loads the operating memory from the internal eeprom, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both pwm channels if applicable. store_user_all, mfr_compare_user_all and restore_user_all commands are disabled if the die exceeds 130c and are not re-enabled until the die temperature drops below 125c. this write-only command has no data bytes. mfr_compare_user_all the mfr_compare_user_all command instructs the pmbus device to compare current command contents with what is stored in non-volatile memory. if the compare operation detects differences, a cml fault will be generated. this write-only command has no data bytes. fault logging command name cmd code description type paged d ata format units eeprom default value mfr_fault_log 0xee fault log data bytes. r block n cf y na mfr_fault_log_ store 0xea command a transfer of the fault log from ram to eeprom. send byte n na mfr_fault_log_clear 0xec initialize the eeprom block reserved for fault logging. send byte n na mfr_fault_log the mfr_fault_log command allows the user to read the contents of the fault_log after the first fault occurrence since the last mfr_fault_log_clear command was written. the contents of this command are stored in non-volatile memory, and are cleared by the mfr_fault_log_clear command. the length and content of this command are listed ltc 3886 3886f 108 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails in table 13. if the user accesses the mfr_fault_log command and no fault log is present, the command will return a data length of 0. if a fault log is present, the mfr_fault_log will return a block of data 147 bytes long. if a fault occurs within the first second of applying power, some of the earlier pages in the fault log may not contain valid data. note: the approximate transfer time for this command is 3.4ms using a 400khz clock. this read-only command is in block format. mfr_fault_log_store the mfr_fault_log_store command forces the fault log operation to be written to eeprom just as if a fault event occurred. this command will set bit 3 of the status_mfr_specific fault if bit 7 enable fault logging is set in the mfr_config_all_ lt c 3886 command. if the die temperature exceeds 130 c, the mfr_fault_log_store command is disabled until the ic temperature drops below 125c. this write-only command has no data bytes. table 13. fault logging this table outlines the format of the block data from a read block data of the mfr_fault_log command. data format definitions lin 11 = pmbus = rev 1.1, part 2, section 7.1 lin 16 = pmbus rev 1.1, part 2, section 8. mantissa portion only byte = 8 bits interpreted per definition of this command d ata bits d ata format byte num block read command block length by te 147 the mfr_fault_log command is a fixed length of 147 bytes the block length will be zero if a data log event has not been captured header information fault log preface [7:0] asc 0 returns ltxx beginning at byte 0 if a partial or complete fault log exists. word xx is a factory identifier that may vary part to part. [7:0] 1 [15:8] reg 2 [7:0] 3 fault source [7:0] reg 4 refer to table 13a. mfr_real_time [7:0] reg 5 48 bit share-clock counter value when fault occurred (200s resolution). [15:8] 6 [23:16] 7 [31:24] 8 [39:32] 9 [47:40] 10 mfr_vout_peak (page 0) [15:8] l16 11 peak read_vout on channel 0 since last power-on or clear_peaks command. [7:0] 12 mfr_vout_peak (page 1) [15:8] l16 13 peak read_vout on channel 1 since last power-on or clear_peaks command. [7:0] 14 mfr_iout_peak (page 0) [15:8] l11 15 peak read_iout on channel 0 since last power-on or clear_peaks command. [7:0] 16 ltc 3886 3886f 109 for more information www.linear.com/ltc3886 mfr_iout_peak (page 1) [15:8] l11 17 peak read_iout on channel 1 since last power-on or clear_peaks command. [7:0] 18 mfr_vin_peak [15:8] l11 19 peak read_vin since last power-on or clear_peaks command. [7:0] 20 read_temperature1 (page 0) [15:8] l11 21 external temperature sensor 0 during last event. [7:0] 22 read_temperature1 (page 1) [15:8] l11 23 external temperature sensor 1 during last event. [7:0] 24 read_temperature2 [15:8] l11 25 ltc3886 die temperature sensor during last event. [7:0] 26 cyclical d ata event n (data at which fault occurred; most recent data) event n represents one complete cycle of adc reads through the mux at time of fault. example: if the fault occurs when the adc is processing step 15, it will continue to take readings through step 25 and then store the header and all 6 event pages to eeprom read_vout (page 0) [15:8] lin 16 27 [7:0] lin 16 28 read_vout (page 1) [15:8] lin 16 29 [7:0] lin 16 30 read_iout (page 0) [15:8] lin 11 31 [7:0] lin 11 32 read_iout (page 1) [15:8] lin 11 33 [7:0] lin 11 34 read_vin [15:8] lin 11 35 [7:0] lin 11 36 read_iin [15:8] lin 11 37 [7:0] lin 11 38 status_vout (page 0) byte 39 status_vout (page 1) byte 40 status_word (page 0) [15:8] word 41 [7:0] word 42 status_word (page 1) [15:8] word 43 [7:0] word 44 status_mfr_specific (page 0) byte 45 status_mfr_specific (page 1) byte 46 event n-1 (data measured before fault was detected) read_vout (page 0) [15:8] lin 16 47 [7:0] lin 16 48 read_vout (page 1) [15:8] lin 16 49 [7:0] lin 16 50 read_iout (page 0) [15:8] lin 11 51 [7:0] lin 11 52 p m b us c o mm an d de t ails ltc 3886 3886f 110 for more information www.linear.com/ltc3886 read_iout (page 1) [15:8] lin 11 53 [7:0] lin 11 54 read_vin [15:8] lin 11 55 [7:0] lin 11 56 read_iin [15:8] lin 11 57 [7:0] lin 11 58 status_vout (page 0) byte 59 status_vout (page 1) byte 60 status_word (page 0) [15:8] word 61 [7:0] word 62 status_word (page 1) [15:8] word 63 [7:0] word 64 status_mfr_specific (page 0) byte 65 status_mfr_specific (page 1) byte 66 * * * event n-5 (oldest recorded data) read_vout (page 0) [15:8] lin 16 127 [7:0] lin 16 128 read_vout (page 1) [15:8] lin 16 129 [7:0] lin 16 130 read_iout (page 0) [15:8] lin 11 131 [7:0] lin 11 132 read_iout (page 1) [15:8] lin 11 133 [7:0] lin 11 134 read_vin [15:8] lin 11 135 [7:0] lin 11 136 read_iin [15:8] lin 11 137 [7:0] lin 11 138 status_vout (page 0) byte 139 status_vout (page 1) byte 140 status_word (page 0) [15:8] word 141 [7:0] word 142 status_word (page 1) [15:8] word 143 [7:0] word 144 status_mfr_specific (page 0) byte 145 status_mfr_specific (page 1) byte 146 p m b us c o mm an d de t ails ltc 3886 3886f 111 for more information www.linear.com/ltc3886 p m b us c o mm an d de t ails table 13a: explanation of position_fault values position_fault value source of fault log 0xff mfr_fault_log_store 0x00 ton_max_fault channel 0 0x01 vout_ov_fault channel 0 0x02 vout_uv_fault channel 0 0x03 iout_oc_fault channel 0 0x05 temp_ot_fault channel 0 0x06 temp_ut_fault channel 0 0x07 vin_ov_fault 0x0a mfr_temperature_2_ot_fault 0x10 ton_max_fault channel 1 0x11 vout_ov_fault channel 1 0x12 vout_uv_fault channel 1 0x13 iout_oc_fault channel 1 0x15 ot_fault channel 1 0x16 ut_fault channel 1 0x17 vin_ov_fault 0x1a mfr_temperature_2_ot_fault mfr_fault_log_clear the mfr_fault_log_clear command will erase the fault log file stored values. it will also clear bit 3 in the status_mfr_specific command. after a clear is issued, the status can take up to 8ms to clear. this write-only command is send bytes. block memory write/read command name cmd code description type paged d ata format units eeprom default value mfr_ee_unlock 0xbd unlock user eeprom for access by mfr_ee_erase and mfr_ee_ data commands. r/w byte n reg na mfr_ee_erase 0xbe initialize user eeprom for bulk programming by mfr_ee_ data . r/w byte n reg na mfr_ee_ data 0xbf data transferred to and from eeprom using sequential pmbus word reads or writes. supports bulk programming. r/w word n reg na all the eeprom commands are disabled if the die temperature exceeds 130 c. eeprom commands are re-enabled when the die temperature drops below 125c. mfr_ee_xxxx the mfr_ee_xxxx commands facilitate bulk programming of the ltc3886 internal eeprom. contact the factory for details. ltc 3886 3886f 112 for more information www.linear.com/ltc3886 typical a pplica t ions high efficiency 150khz/5v and 12v step-down converter with dcr sense 20k 17.8k 10k 23.2k 10k 23.2k 10k 23.2k 24.9k 4.32k intv cc tg0 tg1 boost0 boost1 sw0 sw1 bg0 sync pgood0 pgood1 sda scl v out0_cfg v dd25 v out1_cfg asel0 asel1 freq_cfg v dd33 alert fault0 fault1 share_clk run0 run1 wp phas_cfg 5k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k v sense0 + v sense0 ? i th0 i thr0 v sense1 extv cc i th1 i thr1 bg1 tsns0 0.22f 6.81k 7.5k 1f 220pf 10nf 10nf v out1 12v 10a 530f 530f 3886 ta02 4700pf v out0 5v 15a 2200pf l0: wrth 7443630310 3.1h l1: wrth 7443556680 6.8h m1, m2: renesas rjk0651dpb m3, m4: renesas rjk0653dpb 0.22f tsns1 i sense0 + i sense1 + i sense0 ? i sense1 ? 10f 1f d1 d2 5m 10f 22f 2 v in 18v to 48v 0.1f 0.1f l0 3.1h 6.81k 7.5k 1f m1 m3 m2 m4 1f v in ltc3886 gnd v dd33 v dd25 i in + i in ? l1 6.8h 1f 220pf + + ltc 3886 3886f 113 for more information www.linear.com/ltc3886 typical a pplica t ions 20k 17.8k 20k 17.8k 10k 23.2k 10k 23.2k 20k 15k intv cc tg0 tg1 boost0 boost1 sw0 sw1 bg0 sync pgood0 pgood1 sda scl v out0_cfg v dd25 v out1_cfg asel0 asel1 freq_cfg v dd33 alert fault0 fault1 share_clk run0 run1 wp phas_cfg 5k 10k 10k 10k 10k 10k 10k 10k 30 30 v sense0 + v sense0 ? i th0 i thr0 v sense1 extv cc i th1 i thr1 bg1 tsns0 1000pf 1f 220pf 10nf 10nf v out1 5v 50a 530f 530f 3886 ta03 2200pf l0, l1, l2, l3: wrth 7443556260 2.6h m1, m2, m5, m6: renesas rjk0651dpb m3, m4, m7, m8: renesas rjk0653dpb 1000pf 30 tsns1 i sense0 + i sense1 + i sense0 ? i sense1 ? 10f 1f d1 d2 5m 10f 22f 2 v in 48v 0.1f 0.1f l0 2.6h m1 m3 m2 m4 v in ltc3886 gnd v dd33 v dd25 i in + i in ? l1 2.6h 1f + + 0.002 0.002 30 intv cc tg0 tg1 boost0 boost1 sw0 sw1 bg0 30 30 bg1 1000pf 530f 530f 100pf extv cc i th1 i th0 1000pf 100k intv cc _ltc3870 30 i sense0 + i sense1 + i sense0 ? i sense1 ? sync fault0 fault1 run0 run1 ilim phasmd freq mode0 mode1 10f 1f d3 d4 22f 0.1f 0.1f l3 2.6h m5 m7 m6 m8 v in ltc3870 gnd l2 2.6h + + 0.002 0.002 30 high efficiency 425khz 4-phase 5v step-down converter ltc 3886 3886f 114 for more information www.linear.com/ltc3886 typical a pplica t ions high efficiency 250khz 3-phase 2.5v plus 1-phase 5v step-down converter with sense resistors 20k 12.7k 20k 17.8k 10k 23.2k 10k 23.2k 24.9k 11.3k intv cc tg0 tg1 boost0 boost1 sw0 sw1 bg0 sync pgood0 pgood1 sda scl v out0_cfg v dd25 v out1_cfg asel0 asel1 freq_cfg v dd33 alert fault0 fault1 share_clk run0 run1 wp phas_cfg 5k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 30 30 v sense0 + v sense0 ? i th0 i thr0 v sense1 extv cc i th1 i thr1 bg1 tsns0 1000pf 1f 220pf 10nf 10nf v out 5v 10a 530f v out 2.5v 30a 530f 3886 ta04 2200pf 220pf l0, l2, l3: wrth 7443330330 3.3h l1: wrth 7443320470 4.7h m1, m2, m5, m6: renesas rjk0651dpb m3, m4, m7, m8: renesas rjk0653dpb 1000pf 30 tsns1 i sense0 + i sense1 + i sense0 ? i sense1 ? 10f 1f d1 d2 5m 10f 22f 2 v in 48v 0.1f 0.1f l0 3.3h m1 m3 m2 m4 v in ltc3886 gnd v dd33 v dd25 i in + i in ? l1 4.7h 1f 2200pf + + 0.002 0.002 30 intv cc tg0 tg1 boost0 boost1 sw0 sw1 bg0 30 30 bg1 1000pf 530f 530f 100pf extv cc i th1 i th0 1000pf 100k intv cc _ltc3870 30 i sense0 + i sense1 + i sense0 ? i sense1 ? sync fault0 fault1 run0 run1 ilim phasmd freq mode0 mode1 10f 1f d3 d4 22f 0.1f 0.1f l2 3.3h m5 m7 m6 m8 v in ltc3870 gnd l3 3.3h + + 0.002 0.002 30 ltc 3886 3886f 115 for more information www.linear.com/ltc3886 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 7.00 0.10 (2 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.30 typ or 0.35 45c chamfer 0.40 0.10 1.15 ref 5251 1 2 14 15 26 27 40 bottom view?exposed pad top view side view 6.50 ref (2 sides) 8.00 0.10 (2 sides) 5.00 ref 0.75 0.05 0.75 0.05 r = 0.115 typ r = 0.10 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 4.90 0.10 3.90 0.10 0.00 ? 0.05 (ukg52(46)) qfn rev ? 0413 5.00 ref 3.90 0.05 4.90 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 6.10 0.05 7.50 0.05 6.50 ref (2 sides) 7.10 0.05 8.50 0.05 0.25 0.05 0.50 bsc package outline ukg package variation: ukg52(46) 52-lead plastic qfn (7mm 8mm) (reference ltc dwg # 05-08-1947 rev ?) ltc 3886 3886f 116 for more information www.linear.com/ltc3886 ? linear technology corporation 2015 lt 0715 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3886 r ela t e d p ar t s typical a pplica t ion high efficiency 150khz 2-phase12v step-down converter with sense resistors 10k 23.2k 10k 23.2k 10k 23.2k 10k 23.2k 24.9k 4.32k intv cc tg0 tg1 boost0 boost1 sw0 sw1 bg0 sync pgood0 pgood1 sda scl v out0_cfg v dd25 v out1_cfg asel0 asel1 freq_cfg v dd33 alert fault0 fault1 share_clk run0 run1 wp phas_cfg 5k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k v sense0 + v sense0 ? tsns0 i th0 i thr0 v sense1 extv cc tsns1 i th1 i thr1 bg1 1000pf 30 30 1f 10nf 10nf v out 12v 30a 530f 530f 3886 ta05 2200pf l0, l1: wrth 7443557560 5.6h m1, m2: renesas rjk0651dpb m3, m4: renesas rjk0653dpb 1000pf i sense0 + i sense1 + i sense0 ? i sense1 ? 10f 1f d1 d2 5m 10f 22f 2 v in 48v 0.1f 0.1f l0 5.6h 0.002 0.002 m1 m3 m2 m4 v in ltc3886 gnd v dd33 v dd25 i in + i in ? l1 5.6h 1f 220pf + + 30 30 licensed under u.s. patent 7000125 and other related patents worldwide. part number description comments ltc3870 polyphase expander step-down controller with digital power system management v in up to 60v, 0.5v v out 14v, very high output current, accurate current sharing, current mode applications ltm4676a dual 13a or single 26a step-down dc/dc module regulator with digital power management v in up to 26.5v; 0.5v v out (0.5%) 5.4v, 2% i out adc accuracy, fault logging, i 2 c/pmbus interface, 16mm 16mm 5.01mm bga package ltc3887 dual output multiphase step-down dc/dc controller with digital power system management, 70ms start-up v in up to 24v, 0.5v v out0,1 5.5v, 70ms start-up, analog control loop, i 2 c/pmbus interface with eeprom and 16-bit adc ltc3883/ ltc3883-1 single phase step-down dc/dc controller with digital power system management v in up to 24v, 0.5v v out 5.5v, input current sense amplifier, i 2 c/pmbus interface with eeprom and 16-bit adc ltc3882 dual output multiphase step-down dc/dc voltage mode controller with digital power system management v in up to 38v, 0.5v v out1,2 5.25v, 0.5% v out accuracy i 2 c/pmbus interface with eeprom and 16-bit adc ltc3892/ ltc3892-1 60v, low i q , dual, 2-phase synchronous step-down dc/dc controller v in up to 60v, 0.8v v out 99%?v in , 29a quiescent current adjustable gate drive voltage ltc2977 8-channel pubis power system manager featuring accurate output voltage measurement sequence and super vise eight power supplies margin or trim supplies to 0.25% accuracy ltc 3886 3886f |
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